Standardize clock parameter names to 'clock'.

Fix description for Bus clock_ratio (no longer a ratio).
Add Clock param type (generic Frequency or Latency).

cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/beta_cpu/alpha_full_cpu_builder.cc:
cpu/simple_cpu/simple_cpu.cc:
dev/ide_ctrl.cc:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/pciconfigall.cc:
dev/sinic.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
sim/universe.cc:
    Standardize clock parameter names to 'clock'.
    Fix description for Bus clock_ratio (no longer a ratio).
python/m5/config.py:
    Minor tweaks on Frequency/Latency:
    - added new Clock param type to avoid ambiguities
    - factored out init code into getLatency()
    - made RootFrequency *not* a subclass of Frequency so it
    can't be directly assigned to a Frequency paremeter

--HG--
extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506

python/m5/objects/BaseCPU.py

@@ -25,4 +25,4 @@ class BaseCPU(SimObject):
     defer_registration = Param.Bool(False,
         "defer registration with system (for sampling)")
 
-    cycle_time = Param.Latency(Parent.frequency.latency, "clock speed")
+    clock = Param.Clock(Parent.clock, "clock speed")

python/m5/objects/BaseCache.py

@@ -11,7 +11,7 @@ class BaseCache(BaseMem):
     block_size = Param.Int("block size in bytes")
     compressed_bus = Param.Bool(False,
         "This cache connects to a compressed memory")
-    compression_latency = Param.Latency(0,
+    compression_latency = Param.Latency('0ns',
         "Latency in cycles of compression algorithm")
     do_copy = Param.Bool(False, "perform fast copies in the cache")
     hash_delay = Param.Int(1, "time in cycles of hash access")

python/m5/objects/BaseSystem.py

@@ -2,7 +2,7 @@ from m5 import *
 class BaseSystem(SimObject):
     type = 'BaseSystem'
     abstract = True
-    boot_cpu_frequency = Param.Frequency(Self.cpu[0].cycle_time.frequency,
+    boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
                                          "boot processor frequency")
     memctrl = Param.MemoryController(Parent.any, "memory controller")
     physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")

python/m5/objects/Bus.py

@@ -3,5 +3,5 @@ from BaseHier import BaseHier
 
 class Bus(BaseHier):
     type = 'Bus'
-    clock_ratio = Param.Frequency("ratio of CPU to bus frequency")
+    clock = Param.Clock("bus frequency")
     width = Param.Int("bus width in bytes")

python/m5/objects/Ethernet.py

@@ -58,7 +58,7 @@ class NSGigE(PciDevice):
     hardware_address = Param.EthernetAddr(NextEthernetAddr,
         "Ethernet Hardware Address")
 
-    cycle_time = Param.Frequency('100MHz', "State machine processor frequency")
+    clock = Param.Clock('100MHz', "State machine processor frequency")
 
     dma_data_free = Param.Bool(False, "DMA of Data is free")
     dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
@@ -95,7 +95,7 @@ class Sinic(PciDevice):
     hardware_address = Param.EthernetAddr(NextEthernetAddr,
         "Ethernet Hardware Address")
 
-    cycle_time = Param.Frequency('100MHz', "State machine processor frequency")
+    clock = Param.Clock('100MHz', "State machine processor frequency")
 
     dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
     dma_read_factor = Param.Latency('0us', "multiplier for dma reads")

python/m5/objects/Root.py

@@ -6,7 +6,7 @@ from Trace import Trace
 
 class Root(SimObject):
     type = 'Root'
-    frequency = Param.RootFrequency('200MHz', "tick frequency")
+    clock = Param.RootClock('200MHz', "tick frequency")
     output_file = Param.String('cout', "file to dump simulator output to")
     checkpoint = Param.String('', "checkpoint file to load")
 #    hier = Param.HierParams(HierParams(do_data = False, do_events = True),