8031cd93b5
Fix description for Bus clock_ratio (no longer a ratio).
Add Clock param type (generic Frequency or Latency).
cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/beta_cpu/alpha_full_cpu_builder.cc:
cpu/simple_cpu/simple_cpu.cc:
dev/ide_ctrl.cc:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/pciconfigall.cc:
dev/sinic.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
sim/universe.cc:
Standardize clock parameter names to 'clock'.
Fix description for Bus clock_ratio (no longer a ratio).
python/m5/config.py:
Minor tweaks on Frequency/Latency:
- added new Clock param type to avoid ambiguities
- factored out init code into getLatency()
- made RootFrequency *not* a subclass of Frequency so it
can't be directly assigned to a Frequency paremeter
--HG--
extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506
29 lines
1.1 KiB
Python
29 lines
1.1 KiB
Python
from m5 import *
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class BaseCPU(SimObject):
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type = 'BaseCPU'
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abstract = True
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icache = Param.BaseMem(NULL, "L1 instruction cache object")
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dcache = Param.BaseMem(NULL, "L1 data cache object")
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if build_env['FULL_SYSTEM']:
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dtb = Param.AlphaDTB("Data TLB")
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itb = Param.AlphaITB("Instruction TLB")
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mem = Param.FunctionalMemory("memory")
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system = Param.BaseSystem(Parent.any, "system object")
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else:
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workload = VectorParam.Process("processes to run")
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max_insts_all_threads = Param.Counter(0,
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"terminate when all threads have reached this inst count")
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max_insts_any_thread = Param.Counter(0,
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"terminate when any thread reaches this inst count")
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max_loads_all_threads = Param.Counter(0,
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"terminate when all threads have reached this load count")
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max_loads_any_thread = Param.Counter(0,
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"terminate when any thread reaches this load count")
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defer_registration = Param.Bool(False,
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"defer registration with system (for sampling)")
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clock = Param.Clock(Parent.clock, "clock speed")
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