derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-vega: Improve FLAT disassembly

Browse Source 
Use the opSelectorToRegSym which will print the full range of VGPRs
(e.g., will now print v[2:3] instead of v2 when the source / dest is
64-bits). Fixes atomic disassembly prints. Now shows "glc" if GLC bit is
enabled. Fixes some VGPR fields being printed as an SGPR in places where
the 9-bit register index bit is implied (e.g., VDST).

This makes it easier to use a GPUExec trace to match with LLVM
disassembly when debugging.

Change-Id: Ia163774850f0054243907aca8fc8d0361e37fdd5
This commit is contained in:
Matthew Poremba
2023-12-08 12:39:11 -06:00
parent bc69ab0a1f
commit 7e1b27969f
1 changed files with 40 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

61
src/arch/amdgpu/vega/insts/op_encodings.cc
View File

@@ -1847,10 +1847,10 @@ namespace VegaISA
// One of the flat subtypes should be specified via flags
assert(isFlat() ^ isFlatGlobal() ^ isFlatScratch());
if (isFlat()) {
generateFlatDisassembly();
} else if (isFlatGlobal() || isFlatScratch()) {
if (isFlatGlobal() || isFlatScratch()) {
generateGlobalScratchDisassembly();
} else if (isFlat()) {
generateFlatDisassembly();
} else {
panic("Unknown flat subtype!\n");
}
@@ -1862,13 +1862,19 @@ namespace VegaISA
std::stringstream dis_stream;
dis_stream << _opcode << " ";
if (isLoad())
dis_stream << "v" << extData.VDST << ", ";
if (isLoad() || isAtomic()) {
int dst_size = getOperandSize(numSrcRegOperands()) / 4;
dis_stream << opSelectorToRegSym(extData.VDST + 0x100, dst_size)
<< ", ";
}
dis_stream << "v[" << extData.ADDR << ":" << extData.ADDR + 1 << "]";
dis_stream << opSelectorToRegSym(extData.ADDR + 0x100, 2);
if (isStore())
dis_stream << ", v" << extData.DATA;
if (isStore() || isAtomic()) {
int src_size = getOperandSize(1) / 4;
dis_stream << ", "
<< opSelectorToRegSym(extData.DATA + 0x100, src_size);
}
disassembly = dis_stream.str();
}
@@ -1888,25 +1894,38 @@ namespace VegaISA
std::stringstream dis_stream;
dis_stream << global_opcode << " ";
if (isLoad())
dis_stream << "v" << extData.VDST << ", ";
if (isLoad() || isAtomic()) {
// dest is the first operand after all the src operands
int dst_size = getOperandSize(numSrcRegOperands()) / 4;
dis_stream << opSelectorToRegSym(extData.VDST + 0x100, dst_size)
<< ", ";
}
if (extData.SADDR == 0x7f)
dis_stream << "v[" << extData.ADDR << ":" << extData.ADDR+1 << "]";
else
dis_stream << "v" << extData.ADDR;
if (extData.SADDR == 0x7f) {
dis_stream << opSelectorToRegSym(extData.ADDR + 0x100, 2);
} else {
dis_stream << opSelectorToRegSym(extData.ADDR + 0x100, 1);
}
if (isStore())
dis_stream << ", v" << extData.DATA;
if (isStore() || isAtomic()) {
int src_size = getOperandSize(1) / 4;
dis_stream << ", "
<< opSelectorToRegSym(extData.DATA + 0x100, src_size);
}
if (extData.SADDR == 0x7f)
if (extData.SADDR == 0x7f) {
dis_stream << ", off";
else
dis_stream << ", s[" << extData.SADDR << ":" << extData.SADDR+1
<< "]";
} else {
dis_stream << ", " << opSelectorToRegSym(extData.SADDR, 2);
}
if (instData.OFFSET)
if (instData.OFFSET) {
dis_stream << " offset:" << instData.OFFSET;
}
if (instData.GLC) {
dis_stream << " glc";
}
disassembly = dis_stream.str();
}