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Give each resource in InOrder it's own TraceFlag instead of just standard 'Resource' flag

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This commit is contained in:
Korey Sewell
2009-03-04 13:17:09 -05:00
parent 30cd2d21fa
commit 7c8d544216
11 changed files with 87 additions and 77 deletions
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17
src/cpu/inorder/SConscript
View File

@@ -36,18 +36,29 @@ if 'InOrderCPU' in env['CPU_MODELS']:
TraceFlag('ResReqCount')
TraceFlag('FreeList')
TraceFlag('InOrderCachePort')
TraceFlag('InOrderStage')
TraceFlag('InOrderStall')
TraceFlag('InOrderCPU')
TraceFlag('InOrderMDU')
TraceFlag('RegDepMap')
TraceFlag('InOrderDynInst')
TraceFlag('Resource')
TraceFlag('InOrderAGEN')
TraceFlag('InOrderFetchSeq')
TraceFlag('InOrderTLB')
TraceFlag('InOrderCachePort')
TraceFlag('InOrderBPred')
TraceFlag('InOrderDecode')
TraceFlag('InOrderExecute')
TraceFlag('InOrderInstBuffer')
TraceFlag('InOrderUseDef')
TraceFlag('InOrderMDU')
TraceFlag('InOrderGraduation')
TraceFlag('RefCount')
CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 'InOrderCPU',
'InOrderMDU', 'InOrderCachePort', 'RegDepMap', 'Resource'])
'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB', 'InOrderBPred',
'InOrderDecode', 'InOrderExecute', 'InOrderInstBuffer', 'InOrderUseDef',
'InOrderGraduation', 'InOrderCachePort', 'RegDepMap', 'Resource'])
Source('pipeline_traits.cc')
Source('inorder_dyn_inst.cc')

8
src/cpu/inorder/resources/agen_unit.cc
View File

@@ -54,7 +54,7 @@ AGENUnit::execute(int slot_num)
{
// Load/Store Instruction
if (inst->isMemRef()) {
DPRINTF(Resource, "[tid:%i] Generating Address for [sn:%i] (%s).\n",
DPRINTF(InOrderAGEN, "[tid:%i] Generating Address for [sn:%i] (%s).\n",
tid, inst->seqNum, inst->staticInst->getName());
@@ -67,13 +67,13 @@ AGENUnit::execute(int slot_num)
inst->setMemAddr(inst->getEA());
//inst->setExecuted();
DPRINTF(Resource, "[tid:%i] [sn:%i] Effective address calculated to be: "
DPRINTF(InOrderAGEN, "[tid:%i] [sn:%i] Effective address calculated to be: "
"%#x.\n", tid, inst->seqNum, inst->getEA());
} else if (inst->isStore()) {
fault = inst->calcEA();
inst->setMemAddr(inst->getEA());
DPRINTF(Resource, "[tid:%i] [sn:%i] Effective address calculated to be: "
DPRINTF(InOrderAGEN, "[tid:%i] [sn:%i] Effective address calculated to be: "
"%#x.\n", tid, inst->seqNum, inst->getEA());
} else {
panic("Unexpected memory type!\n");
@@ -86,7 +86,7 @@ AGENUnit::execute(int slot_num)
}
}
} else {
DPRINTF(Resource, "[tid:] Ignoring non-memory instruction [sn:%i].\n", tid, seq_num);
DPRINTF(InOrderAGEN, "[tid:] Ignoring non-memory instruction [sn:%i].\n", tid, seq_num);
agen_req->done();
}
}

10
src/cpu/inorder/resources/branch_predictor.cc
View File

@@ -90,7 +90,7 @@ BranchPredictor::execute(int slot_num)
predictedTaken++;
} else {
DPRINTF(Resource, "[tid:%i]: [sn:%i]: Branch predicted false.\n",
DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Branch predicted false.\n",
tid, seq_num);
if (inst->isCondDelaySlot())
@@ -105,11 +105,11 @@ BranchPredictor::execute(int slot_num)
inst->setBranchPred(predict_taken);
DPRINTF(Resource, "[tid:%i]: [sn:%i]: Predicted PC is %08p.\n",
DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Predicted PC is %08p.\n",
tid, seq_num, pred_PC);
} else {
DPRINTF(Resource, "[tid:%i]: Ignoring [sn:%i] because this isn't "
DPRINTF(InOrderBPred, "[tid:%i]: Ignoring [sn:%i] because this isn't "
"a control instruction.\n", tid, seq_num);
}
@@ -119,7 +119,7 @@ BranchPredictor::execute(int slot_num)
case UpdatePredictor:
{
DPRINTF(Resource, "[tid:%i]: [sn:%i]: Updating Branch Predictor.\n",
DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Updating Branch Predictor.\n",
tid, seq_num);
@@ -138,7 +138,7 @@ void
BranchPredictor::squash(DynInstPtr inst, int squash_stage,
InstSeqNum squash_seq_num, unsigned tid)
{
DPRINTF(Resource, "Squashing...\n");
DPRINTF(InOrderBPred, "Squashing...\n");
branchPred.squash(squash_seq_num, tid);
}

1
src/cpu/inorder/resources/branch_predictor.hh
View File

@@ -41,7 +41,6 @@
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/resources/bpred_unit.hh"
#include "cpu/inorder/cpu.hh"
//#include "cpu/inorder/params.hh"
class BranchPredictor : public Resource {
public:

4
src/cpu/inorder/resources/decode_unit.cc
View File

@@ -63,7 +63,7 @@ DecodeUnit::execute(int slot_num)
bool done_sked = ThePipeline::createBackEndSchedule(inst);
if (done_sked) {
DPRINTF(Resource, "[tid:%i]: Setting Destination Register(s) for [sn:%i].\n",
DPRINTF(InOrderDecode, "[tid:%i]: Setting Destination Register(s) for [sn:%i].\n",
tid, seq_num);
regDepMap[tid]->insert(inst);
decode_req->done();
@@ -85,7 +85,7 @@ DecodeUnit::execute(int slot_num)
void
DecodeUnit::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid)
{
DPRINTF(Resource, "[tid:%i]: Updating due to squash from stage %i after [sn:%i].\n",
DPRINTF(InOrderDecode, "[tid:%i]: Updating due to squash from stage %i after [sn:%i].\n",
tid, stage_num, squash_seq_num);
//cpu->removeInstsUntil(squash_seq_num, tid);

16
src/cpu/inorder/resources/execution_unit.cc
View File

@@ -68,7 +68,7 @@ ExecutionUnit::execute(int slot_num)
exec_req->fault = NoFault;
DPRINTF(Resource, "[tid:%i] Executing [sn:%i] [PC:%#x] .\n",
DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%#x] .\n",
tid, seq_num, inst->readPC());
switch (exec_req->cmd)
@@ -99,7 +99,7 @@ ExecutionUnit::execute(int slot_num)
inst->bdelaySeqNum = seq_num;
inst->setPredTarg(inst->nextPC);
DPRINTF(Resource, "[tid:%i]: Conditional branch inst"
DPRINTF(InOrderExecute, "[tid:%i]: Conditional branch inst"
"[sn:%i] PC %#x mispredicted as taken.\n", tid,
seq_num, inst->PC);
} else if (!inst->predTaken() && inst->isCondDelaySlot()) {
@@ -107,13 +107,13 @@ ExecutionUnit::execute(int slot_num)
inst->setPredTarg(inst->nextPC);
inst->procDelaySlotOnMispred = true;
DPRINTF(Resource, "[tid:%i]: Conditional branch inst."
DPRINTF(InOrderExecute, "[tid:%i]: Conditional branch inst."
"[sn:%i] PC %#x mispredicted as not taken.\n", tid,
seq_num, inst->PC);
} else {
inst->bdelaySeqNum = seq_num + 1;
DPRINTF(Resource, "[tid:%i]: Misprediction detected at "
DPRINTF(InOrderExecute, "[tid:%i]: Misprediction detected at "
"[sn:%i] PC %#x,\n\t squashing after delay slot "
"instruction [sn:%i].\n",
tid, seq_num, inst->PC, inst->bdelaySeqNum);
@@ -122,20 +122,20 @@ ExecutionUnit::execute(int slot_num)
inst->setPredTarg(inst->nextNPC);
}
DPRINTF(Resource, "[tid:%i] Redirecting fetch to %#x.\n", tid,
DPRINTF(InOrderExecute, "[tid:%i] Redirecting fetch to %#x.\n", tid,
inst->readPredTarg());
} else if(inst->isIndirectCtrl()){
inst->setPredTarg(inst->nextNPC);
inst->bdelaySeqNum = seq_num + 1;
DPRINTF(Resource, "[tid:%i] Redirecting fetch to %#x.\n", tid,
DPRINTF(InOrderExecute, "[tid:%i] Redirecting fetch to %#x.\n", tid,
inst->readPredTarg());
} else {
panic("Non-control instruction (%s) mispredicting?!!",
inst->staticInst->getName());
}
DPRINTF(Resource, "[tid:%i] Squashing will start from stage %i.\n",
DPRINTF(InOrderExecute, "[tid:%i] Squashing will start from stage %i.\n",
tid, stage_num);
cpu->pipelineStage[stage_num]->squashDueToBranch(inst, tid);
@@ -164,7 +164,7 @@ ExecutionUnit::execute(int slot_num)
inst->setExecuted();
exec_req->done();
DPRINTF(Resource, "[tid:%i]: The result of execution is 0x%x.\n",
DPRINTF(InOrderExecute, "[tid:%i]: The result of execution is 0x%x.\n",
inst->readTid(), inst->readIntResult(0));
} else {
warn("inst [sn:%i] had a %s fault", seq_num, fault->name());

28
src/cpu/inorder/resources/fetch_seq_unit.cc
View File

@@ -90,7 +90,7 @@ FetchSeqUnit::execute(int slot_num)
delaySlotInfo[tid].targetReady = false;
DPRINTF(Resource, "[tid:%i]: Setting PC to delay slot target\n",tid);
DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to delay slot target\n",tid);
}
inst->setPC(PC[tid]);
@@ -102,7 +102,7 @@ FetchSeqUnit::execute(int slot_num)
inst->setMemAddr(PC[tid]);
inst->setSeqNum(cpu->getAndIncrementInstSeq(tid));
DPRINTF(Resource, "[tid:%i]: Assigning [sn:%i] to PC %08p\n", tid,
DPRINTF(InOrderFetchSeq, "[tid:%i]: Assigning [sn:%i] to PC %08p\n", tid,
inst->seqNum, inst->readPC());
if (delaySlotInfo[tid].numInsts > 0) {
@@ -113,7 +113,7 @@ FetchSeqUnit::execute(int slot_num)
delaySlotInfo[tid].targetReady = true;
}
DPRINTF(Resource, "[tid:%i]: %i delay slot inst(s) left to"
DPRINTF(InOrderFetchSeq, "[tid:%i]: %i delay slot inst(s) left to"
" process.\n", tid, delaySlotInfo[tid].numInsts);
}
@@ -139,11 +139,11 @@ FetchSeqUnit::execute(int slot_num)
pcBlockStage[tid] = stage_num;
} else if (inst->isCondDelaySlot() && !inst->predTaken()) {
// Not-Taken AND Conditional Control
DPRINTF(Resource, "[tid:%i]: [sn:%i]: [PC:%08p] Predicted Not-Taken Cond. "
DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: [PC:%08p] Predicted Not-Taken Cond. "
"Delay inst. Skipping delay slot and Updating PC to %08p\n",
tid, inst->seqNum, inst->readPC(), inst->readPredTarg());
DPRINTF(Resource, "[tid:%i] Setting up squash to start from stage %i, after [sn:%i].\n",
DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to start from stage %i, after [sn:%i].\n",
tid, stage_num, seq_num);
inst->bdelaySeqNum = seq_num;
@@ -152,7 +152,7 @@ FetchSeqUnit::execute(int slot_num)
squashAfterInst(inst, stage_num, tid);
} else if (!inst->isCondDelaySlot() && !inst->predTaken()) {
// Not-Taken Control
DPRINTF(Resource, "[tid:%i]: [sn:%i]: Predicted Not-Taken Control "
DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Predicted Not-Taken Control "
"inst. updating PC to %08p\n", tid, inst->seqNum,
inst->readNextPC());
@@ -166,11 +166,11 @@ FetchSeqUnit::execute(int slot_num)
delaySlotInfo[tid].targetReady = false;
delaySlotInfo[tid].targetAddr = inst->readPredTarg();
DPRINTF(Resource, "[tid:%i]: [sn:%i] Updating delay slot target "
DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i] Updating delay slot target "
"to PC %08p\n", tid, inst->seqNum, inst->readPredTarg());
// Set-Up Squash Through-Out Pipeline
DPRINTF(Resource, "[tid:%i] Setting up squash to start from stage %i, after [sn:%i].\n",
DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to start from stage %i, after [sn:%i].\n",
tid, stage_num, seq_num + 1);
inst->bdelaySeqNum = seq_num + 1;
inst->squashingStage = stage_num;
@@ -179,7 +179,7 @@ FetchSeqUnit::execute(int slot_num)
squashAfterInst(inst, stage_num, tid);
}
} else {
DPRINTF(Resource, "[tid:%i]: [sn:%i]: Ignoring branch target update "
DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Ignoring branch target update "
"since then is not a control instruction.\n", tid, inst->seqNum);
}
@@ -209,7 +209,7 @@ void
FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
InstSeqNum squash_seq_num, unsigned tid)
{
DPRINTF(Resource, "[tid:%i]: Updating due to squash from stage %i.\n",
DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating due to squash from stage %i.\n",
tid, squash_stage);
InstSeqNum done_seq_num = inst->bdelaySeqNum;
@@ -217,7 +217,7 @@ FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
if (squashSeqNum[tid] <= done_seq_num &&
lastSquashCycle[tid] == curTick) {
DPRINTF(Resource, "[tid:%i]: Ignoring squash from stage %i, since"
DPRINTF(InOrderFetchSeq, "[tid:%i]: Ignoring squash from stage %i, since"
"there is an outstanding squash that is older.\n",
tid, squash_stage);
} else {
@@ -237,7 +237,7 @@ FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
nextPC[tid] = new_PC + instSize;
nextNPC[tid] = new_PC + (2 * instSize);
DPRINTF(Resource, "[tid:%i]: Setting PC to %08p.\n",
DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to %08p.\n",
tid, PC[tid]);
} else {
delaySlotInfo[tid].numInsts = 1;
@@ -278,7 +278,7 @@ FetchSeqUnit::FetchSeqEvent::process()
fs_res->PC[i] = fs_res->cpu->readPC(i);
fs_res->nextPC[i] = fs_res->cpu->readNextPC(i);
fs_res->nextNPC[i] = fs_res->cpu->readNextNPC(i);
DPRINTF(Resource, "[tid:%i]: Setting PC:%08p NPC:%08p NNPC:%08p.\n",
DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC:%08p NPC:%08p NNPC:%08p.\n",
fs_res->PC[i], fs_res->nextPC[i], fs_res->nextNPC[i]);
fs_res->pcValid[i] = true;
@@ -299,7 +299,7 @@ FetchSeqUnit::activateThread(unsigned tid)
cpu->fetchPriorityList.push_back(tid);
DPRINTF(Resource, "[tid:%i]: Reading PC:%08p NPC:%08p NNPC:%08p.\n",
DPRINTF(InOrderFetchSeq, "[tid:%i]: Reading PC:%08p NPC:%08p NNPC:%08p.\n",
tid, PC[tid], nextPC[tid], nextNPC[tid]);
}

6
src/cpu/inorder/resources/graduation_unit.cc
View File

@@ -71,14 +71,14 @@ GraduationUnit::execute(int slot_num)
lastCycleGrad = curTick;
numCycleGrad = 0;
} else if (numCycleGrad > width) {
DPRINTF(Resource, "Graduation bandwidth reached for this cycle.\n");
DPRINTF(InOrderGraduation, "Graduation bandwidth reached for this cycle.\n");
return;
}
// Make sure this is the last thing on the resource schedule
assert(inst->resSched.size() == 1);
DPRINTF(Resource, "[tid:%i] Graduating instruction [sn:%i].\n",
DPRINTF(InOrderGraduation, "[tid:%i] Graduating instruction [sn:%i].\n",
tid, seq_num);
DPRINTF(RefCount, "Refcount = %i.\n", 0/*inst->curCount()*/);
@@ -88,7 +88,7 @@ GraduationUnit::execute(int slot_num)
// @TODO: Fix this functionality. Probably too conservative.
if (inst->isNonSpeculative()) {
*nonSpecInstActive[tid] = false;
DPRINTF(Resource, "[tid:%i] Non-speculative instruction [sn:%i] has graduated.\n",
DPRINTF(InOrderGraduation, "[tid:%i] Non-speculative instruction [sn:%i] has graduated.\n",
tid, seq_num);
}

20
src/cpu/inorder/resources/inst_buffer.cc
View File

@@ -76,21 +76,21 @@ InstBuffer::execute(int slot_idx)
bool do_bypass = true;
if (!instList.empty()) {
DPRINTF(Resource, "[sn:%i] cannot bypass stage %i because buffer isn't empty.\n",
DPRINTF(InOrderInstBuffer, "[sn:%i] cannot bypass stage %i because buffer isn't empty.\n",
inst->seqNum, next_stage);
do_bypass = false;
} else if(cpu->pipelineStage[bypass_stage]->isBlocked(tid)) {
DPRINTF(Resource, "[sn:%i] cannot bypass stage %i because stage %i is blocking.\n",
DPRINTF(InOrderInstBuffer, "[sn:%i] cannot bypass stage %i because stage %i is blocking.\n",
inst->seqNum, next_stage);
do_bypass = false;
} else if(cpu->pipelineStage[bypass_stage]->stageBufferAvail() <= 0) {
DPRINTF(Resource, "[sn:%i] cannot bypass stage %i because there is no room in "
DPRINTF(InOrderInstBuffer, "[sn:%i] cannot bypass stage %i because there is no room in "
"stage %i incoming stage buffer.\n", inst->seqNum, next_stage);
do_bypass = false;
}
if (!do_bypass) { // SCHEDULE USAGE OF BUFFER
DPRINTF(Resource, "Scheduling [sn:%i] for buffer insertion in stage %i\n",
DPRINTF(InOrderInstBuffer, "Scheduling [sn:%i] for buffer insertion in stage %i\n",
inst->seqNum, next_stage);
// Add to schedule: Insert into buffer in next stage
@@ -105,7 +105,7 @@ InstBuffer::execute(int slot_idx)
inst->resSched.push(new ScheduleEntry(bypass_stage, stage_pri, id,
InstBuffer::RemoveInst));
} else { // BYPASS BUFFER & NEXT STAGE
DPRINTF(Resource, "Setting [sn:%i] to bypass stage %i and enter stage %i.\n",
DPRINTF(InOrderInstBuffer, "Setting [sn:%i] to bypass stage %i and enter stage %i.\n",
inst->seqNum, next_stage, bypass_stage);
inst->setNextStage(bypass_stage);
instsBypassed++;
@@ -120,12 +120,12 @@ InstBuffer::execute(int slot_idx)
bool inserted = false;
if (instList.size() < width) {
DPRINTF(Resource, "[tid:%i]: Inserting [sn:%i] into buffer.\n",
DPRINTF(InOrderInstBuffer, "[tid:%i]: Inserting [sn:%i] into buffer.\n",
tid, seq_num);
insert(inst);
inserted = true;
} else {
DPRINTF(Resource, "[tid:%i]: Denying [sn:%i] request because "
DPRINTF(InOrderInstBuffer, "[tid:%i]: Denying [sn:%i] request because "
"buffer is full.\n", tid, seq_num);
@@ -144,7 +144,7 @@ InstBuffer::execute(int slot_idx)
case RemoveInst:
{
DPRINTF(Resource, "[tid:%i]: Removing [sn:%i] from buffer.\n",
DPRINTF(InOrderInstBuffer, "[tid:%i]: Removing [sn:%i] from buffer.\n",
tid, seq_num);
remove(inst);
ib_req->done();
@@ -155,7 +155,7 @@ InstBuffer::execute(int slot_idx)
fatal("Unrecognized command to %s", resName);
}
DPRINTF(Resource, "Buffer now contains %i insts.\n", instList.size());
DPRINTF(InOrderInstBuffer, "Buffer now contains %i insts.\n", instList.size());
}
void
@@ -212,7 +212,7 @@ InstBuffer::squash(DynInstPtr inst, int stage_num,
// Removed Instructions from InstList & Clear Remove List
while (!remove_list.empty()) {
DPRINTF(Resource, "[tid:%i]: Removing squashed [sn:%i] from buffer.\n",
DPRINTF(InOrderInstBuffer, "[tid:%i]: Removing squashed [sn:%i] from buffer.\n",
tid, (*remove_list.front())->seqNum);
instList.erase(remove_list.front());
remove_list.pop();

12
src/cpu/inorder/resources/tlb_unit.cc
View File

@@ -102,7 +102,7 @@ TLBUnit::execute(int slot_idx)
cpu->thread[tid]->getTC());
if (tlb_req->fault != NoFault) {
DPRINTF(Resource, "[tid:%i]: %s encountered while translating "
DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating "
"addr:%08p for [sn:%i].\n", tid, tlb_req->fault->name(),
tlb_req->memReq->getVaddr(), seq_num);
//insert(inst);
@@ -114,7 +114,7 @@ TLBUnit::execute(int slot_idx)
// Let CPU handle the fault
cpu->trap(tlb_req->fault, tid);
} else {
DPRINTF(Resource, "[tid:%i]: [sn:%i] virt. addr %08p translated "
DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i] virt. addr %08p translated "
"to phys. addr:%08p.\n", tid, seq_num,
tlb_req->memReq->getVaddr(),
tlb_req->memReq->getPaddr());
@@ -125,7 +125,7 @@ TLBUnit::execute(int slot_idx)
case DataLookup:
{
DPRINTF(Resource, "[tid:%i]: [sn:%i]: Attempting to translate %08p.\n",
DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i]: Attempting to translate %08p.\n",
tid, seq_num, tlb_req->memReq->getVaddr());
tlb_req->fault =
@@ -133,7 +133,7 @@ TLBUnit::execute(int slot_idx)
cpu->thread[tid]->getTC());
if (tlb_req->fault != NoFault) {
DPRINTF(Resource, "[tid:%i]: %s encountered while translating "
DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating "
"addr:%08p for [sn:%i].\n", tid, tlb_req->fault->name(),
tlb_req->memReq->getVaddr(), seq_num);
//insert(inst);
@@ -144,7 +144,7 @@ TLBUnit::execute(int slot_idx)
// Let CPU handle the fault
cpu->trap(tlb_req->fault, tid);
} else {
DPRINTF(Resource, "[tid:%i]: [sn:%i] virt. addr %08p translated "
DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i] virt. addr %08p translated "
"to phys. addr:%08p.\n", tid, seq_num,
tlb_req->memReq->getVaddr(),
tlb_req->memReq->getPaddr());
@@ -169,7 +169,7 @@ TLBUnitEvent::process()
int stage_num = resource->reqMap[slotIdx]->getStageNum();
int tid = inst->threadNumber;
DPRINTF(Resource, "Waking up from TLB Miss caused by [sn:%i].\n",
DPRINTF(InOrderTLB, "Waking up from TLB Miss caused by [sn:%i].\n",
inst->seqNum);
TLBUnit* tlb_res = dynamic_cast<TLBUnit*>(resource);

42
src/cpu/inorder/resources/use_def.cc
View File

@@ -104,7 +104,7 @@ UseDefUnit::execute(int slot_idx)
// in the pipeline then stall instructions here
if (*nonSpecInstActive[tid] == true &&
seq_num > *nonSpecSeqNum[tid]) {
DPRINTF(Resource, "[tid:%i]: [sn:%i] cannot execute because there is "
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i] cannot execute because there is "
"non-speculative instruction [sn:%i] has not graduated.\n",
tid, seq_num, *nonSpecSeqNum[tid]);
return;
@@ -119,7 +119,7 @@ UseDefUnit::execute(int slot_idx)
{
int reg_idx = inst->_srcRegIdx[ud_idx];
DPRINTF(Resource, "[tid:%i]: Attempting to read source register idx %i.\n",
DPRINTF(InOrderUseDef, "[tid:%i]: Attempting to read source register idx %i.\n",
tid, ud_idx);
// Ask register dependency map if it is OK to read from Arch. Reg. File
@@ -127,19 +127,19 @@ UseDefUnit::execute(int slot_idx)
// Read From Register File
if (inst->seqNum <= outReadSeqNum[tid]) {
if (reg_idx <= FP_Base_DepTag) {
DPRINTF(Resource, "[tid:%i]: Reading Int Reg %i from Register File.\n",
DPRINTF(InOrderUseDef, "[tid:%i]: Reading Int Reg %i from Register File.\n",
tid, reg_idx);
inst->setIntSrc(ud_idx,
cpu->readIntReg(reg_idx,inst->readTid()));
} else if (reg_idx <= Ctrl_Base_DepTag) {
reg_idx -= FP_Base_DepTag;
DPRINTF(Resource, "[tid:%i]: Reading Float Reg %i from Register File.\n",
DPRINTF(InOrderUseDef, "[tid:%i]: Reading Float Reg %i from Register File.\n",
tid, reg_idx);
inst->setIntSrc(ud_idx, // Always Read FloatRegBits For Now
cpu->readFloatRegBits(reg_idx, inst->readTid()));
} else {
reg_idx -= Ctrl_Base_DepTag;
DPRINTF(Resource, "[tid:%i]: Reading Misc Reg %i from Register File.\n",
DPRINTF(InOrderUseDef, "[tid:%i]: Reading Misc Reg %i from Register File.\n",
tid, reg_idx);
inst->setIntSrc(ud_idx,
cpu->readMiscReg(reg_idx, inst->readTid()));
@@ -149,7 +149,7 @@ UseDefUnit::execute(int slot_idx)
ud_req->done();
} else {
DPRINTF(Resource, "[tid:%i]: Unable to read because of [sn:%i] hasnt read it's"
DPRINTF(InOrderUseDef, "[tid:%i]: Unable to read because of [sn:%i] hasnt read it's"
" registers yet.\n", tid, outReadSeqNum[tid]);
DPRINTF(InOrderStall, "STALL: [tid:%i]: waiting for [sn:%i] to write\n",
tid, outReadSeqNum[tid]);
@@ -164,19 +164,19 @@ UseDefUnit::execute(int slot_idx)
int dest_reg_idx = forward_inst->getDestIdxNum(reg_idx);
if (reg_idx <= FP_Base_DepTag) {
DPRINTF(Resource, "[tid:%i]: Forwarding dest. reg value 0x%x from "
DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest. reg value 0x%x from "
"[sn:%i] to [sn:%i] source #%i.\n",
tid, forward_inst->readIntResult(dest_reg_idx) ,
forward_inst->seqNum, inst->seqNum, ud_idx);
inst->setIntSrc(ud_idx, forward_inst->readIntResult(dest_reg_idx));
} else if (reg_idx <= Ctrl_Base_DepTag) {
DPRINTF(Resource, "[tid:%i]: Forwarding dest. reg value 0x%x from "
DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest. reg value 0x%x from "
"[sn:%i] to [sn:%i] source #%i.\n",
tid, forward_inst->readFloatResult(dest_reg_idx) ,
forward_inst->seqNum, inst->seqNum, ud_idx);
inst->setFloatSrc(ud_idx, forward_inst->readFloatResult(dest_reg_idx));
} else {
DPRINTF(Resource, "[tid:%i]: Forwarding dest. reg value 0x%x from "
DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest. reg value 0x%x from "
"[sn:%i] to [sn:%i] source #%i.\n",
tid, forward_inst->readIntResult(dest_reg_idx) ,
forward_inst->seqNum, inst->seqNum, ud_idx);
@@ -187,13 +187,13 @@ UseDefUnit::execute(int slot_idx)
ud_req->done();
} else {
DPRINTF(Resource, "[tid:%i]: Unable to read because of [sn:%i] hasnt read it's"
DPRINTF(InOrderUseDef, "[tid:%i]: Unable to read because of [sn:%i] hasnt read it's"
" registers yet.\n", tid, outReadSeqNum[tid]);
DPRINTF(InOrderStall, "STALL: [tid:%i]: waiting for [sn:%i] to forward\n",
tid, outReadSeqNum[tid]);
}
} else {
DPRINTF(Resource, "[tid:%i]: Source register idx: %i is not ready to read.\n",
DPRINTF(InOrderUseDef, "[tid:%i]: Source register idx: %i is not ready to read.\n",
tid, reg_idx);
DPRINTF(InOrderStall, "STALL: [tid:%i]: waiting to read register (idx=%i)\n",
tid, reg_idx);
@@ -208,12 +208,12 @@ UseDefUnit::execute(int slot_idx)
int reg_idx = inst->_destRegIdx[ud_idx];
if (regDepMap[tid]->canWrite(reg_idx, inst)) {
DPRINTF(Resource, "[tid:%i]: Attempting to write to Register File.\n",
DPRINTF(InOrderUseDef, "[tid:%i]: Attempting to write to Register File.\n",
tid);
if (inst->seqNum <= outReadSeqNum[tid]) {
if (reg_idx <= FP_Base_DepTag) {
DPRINTF(Resource, "[tid:%i]: Writing 0x%x to register idx %i.\n",
DPRINTF(InOrderUseDef, "[tid:%i]: Writing 0x%x to register idx %i.\n",
tid, inst->readIntResult(ud_idx), reg_idx);
// Remove Dependencies
@@ -246,13 +246,13 @@ UseDefUnit::execute(int slot_idx)
ud_req->done();
} else {
DPRINTF(Resource, "[tid:%i]: Unable to write because of [sn:%i] hasnt read it's"
DPRINTF(InOrderUseDef, "[tid:%i]: Unable to write because of [sn:%i] hasnt read it's"
" registers yet.\n", tid, outReadSeqNum);
DPRINTF(InOrderStall, "STALL: [tid:%i]: waiting for [sn:%i] to read\n",
tid, outReadSeqNum);
}
} else {
DPRINTF(Resource, "[tid:%i]: Dest. register idx: %i is not ready to write.\n",
DPRINTF(InOrderUseDef, "[tid:%i]: Dest. register idx: %i is not ready to write.\n",
tid, reg_idx);
DPRINTF(InOrderStall, "STALL: [tid:%i]: waiting to write register (idx=%i)\n",
tid, reg_idx);
@@ -270,7 +270,7 @@ UseDefUnit::execute(int slot_idx)
void
UseDefUnit::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid)
{
DPRINTF(Resource, "[tid:%i]: Updating Due To Squash After [sn:%i].\n",
DPRINTF(InOrderUseDef, "[tid:%i]: Updating Due To Squash After [sn:%i].\n",
tid, squash_seq_num);
std::vector<int> slot_remove_list;
@@ -285,7 +285,7 @@ UseDefUnit::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, un
req_ptr->getInst()->readTid() == tid &&
req_ptr->getInst()->seqNum > squash_seq_num) {
DPRINTF(Resource, "[tid:%i]: Squashing [sn:%i].\n",
DPRINTF(InOrderUseDef, "[tid:%i]: Squashing [sn:%i].\n",
req_ptr->getInst()->readTid(),
req_ptr->getInst()->seqNum);
@@ -309,18 +309,18 @@ UseDefUnit::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, un
}
if (outReadSeqNum[tid] >= squash_seq_num) {
DPRINTF(Resource, "[tid:%i]: Outstanding Read Seq Num Reset.\n", tid);
DPRINTF(InOrderUseDef, "[tid:%i]: Outstanding Read Seq Num Reset.\n", tid);
outReadSeqNum[tid] = maxSeqNum;
} else if (outReadSeqNum[tid] != maxSeqNum) {
DPRINTF(Resource, "[tid:%i]: No need to reset Outstanding Read Seq Num %i\n",
DPRINTF(InOrderUseDef, "[tid:%i]: No need to reset Outstanding Read Seq Num %i\n",
tid, outReadSeqNum[tid]);
}
if (outWriteSeqNum[tid] >= squash_seq_num) {
DPRINTF(Resource, "[tid:%i]: Outstanding Write Seq Num Reset.\n", tid);
DPRINTF(InOrderUseDef, "[tid:%i]: Outstanding Write Seq Num Reset.\n", tid);
outWriteSeqNum[tid] = maxSeqNum;
} else if (outWriteSeqNum[tid] != maxSeqNum) {
DPRINTF(Resource, "[tid:%i]: No need to reset Outstanding Write Seq Num %i\n",
DPRINTF(InOrderUseDef, "[tid:%i]: No need to reset Outstanding Write Seq Num %i\n",
tid, outWriteSeqNum[tid]);
}
}