ruby: cache configuration fix to use bytes

Changed cache size to be in bytes instead of kb so that testers can use very
small caches and increase the chance of writeback races.

src/mem/ruby/config/MI_example-homogeneous.rb

@@ -13,7 +13,7 @@ RubySystem.reset
 # default values
 
 num_cores = 2
-l1_cache_size_kb = 32
+l1_cache_size_kb = 32768
 l1_cache_assoc = 8
 l1_cache_latency = 1
 num_memories = 2
@@ -37,6 +37,12 @@ for i in 0..$*.size-1 do
   elsif $*[i] == "-s"
     memory_size_mb = $*[i+1].to_i
     i = i + 1
+  elsif $*[i] == "-C"
+    l1_cache_size_bytes = $*[i+1].to_i
+    i = i + 1
+  elsif $*[i] == "-A"
+    l1_cache_assoc = $*[i+1].to_i
+    i = i + 1
   elsif $*[i] == "-D"
     num_dma = $*[i+1].to_i
     i = i + 1
@@ -51,7 +57,7 @@ assert(protocol == "MI_example", __FILE__ + " cannot be used with protocol " + p
 require protocol+".rb"
 
 num_cores.times { |n|
-  cache = SetAssociativeCache.new("l1u_"+n.to_s, l1_cache_size_kb, l1_cache_latency, l1_cache_assoc, "PSEUDO_LRU")
+  cache = SetAssociativeCache.new("l1u_"+n.to_s, l1_cache_size_bytes, l1_cache_latency, l1_cache_assoc, "PSEUDO_LRU")
   sequencer = Sequencer.new("Sequencer_"+n.to_s, cache, cache)
   iface_ports << sequencer
   net_ports << MI_example_CacheController.new("L1CacheController_"+n.to_s,

src/mem/ruby/config/cfg.rb

@@ -401,17 +401,17 @@ class DMAController < NetPort
 end
 
 class Cache < LibRubyObject
-  attr :size_kb, :latency
+  attr :size, :latency
   attr_writer :controller
-  def initialize(obj_name, size_kb, latency)
+  def initialize(obj_name, size, latency)
     super(obj_name)
-    assert size_kb.is_a?(Integer), "Cache size must be an integer"
-    @size_kb = size_kb
+    assert size.is_a?(Integer), "Cache size must be an integer"
+    @size = size
     @latency = latency
   end
 
   def args
-    "controller "+@controller.obj_name+" size_kb "+@size_kb.to_s+" latency "+@latency.to_s
+    "controller "+@controller.obj_name+" size "+@size.to_s+" latency "+@latency.to_s
   end
 end
 
@@ -422,8 +422,8 @@ class SetAssociativeCache < Cache
   #  when an integer, it represents the number of cycles for a hit
   #  when a float, it represents the cache access time in ns
   #  when set to "auto", libruby will attempt to find a realistic latency by running CACTI
-  def initialize(obj_name, size_kb, latency, assoc, replacement_policy)
-    super(obj_name, size_kb, latency)
+  def initialize(obj_name, size, latency, assoc, replacement_policy)
+    super(obj_name, size, latency)
     @assoc = assoc
     @replacement_policy = replacement_policy
   end
@@ -431,7 +431,7 @@ class SetAssociativeCache < Cache
   def calculateLatency()
     if @latency == "auto"
       cacti_args = Array.new()
-      cacti_args << (@size_kb*1024) <<  RubySystem.block_size_bytes << @assoc
+      cacti_args << (@size) <<  RubySystem.block_size_bytes << @assoc
       cacti_args << 1 << 0 << 0 << 0 << 1
       cacti_args << RubySystem.tech_nm << RubySystem.block_size_bytes*8
       cacti_args << 0 << 0 << 0 << 1 << 0 << 0 << 0 << 0 << 1

src/mem/ruby/system/CacheMemory.cc

@@ -52,12 +52,12 @@ CacheMemory::CacheMemory(const string & name)
 
 void CacheMemory::init(const vector<string> & argv)
 {
-  int cache_size = 0;
+  int cache_size = -1;
   string policy;
 
   m_controller = NULL;
   for (uint32 i=0; i<argv.size(); i+=2) {
-    if (argv[i] == "size_kb") {
+    if (argv[i] == "size") {
       cache_size = atoi(argv[i+1].c_str());
     } else if (argv[i] == "latency") {
       m_latency = atoi(argv[i+1].c_str());
@@ -72,8 +72,12 @@ void CacheMemory::init(const vector<string> & argv)
     }
   }
 
-  m_cache_num_sets = cache_size / m_cache_assoc;
+  assert(cache_size != -1);
+  
+  m_cache_num_sets = (cache_size / m_cache_assoc) / RubySystem::getBlockSizeBytes();
+  assert(m_cache_num_sets > 1);
   m_cache_num_set_bits = log_int(m_cache_num_sets);
+  assert(m_cache_num_set_bits > 0);
 
   if(policy == "PSEUDO_LRU")
     m_replacementPolicy_ptr = new PseudoLRUPolicy(m_cache_num_sets, m_cache_assoc);