derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-arm: Add SECURE_RD/WR flags to miscRegInfo

Browse Source 
The introduction of Secure EL2 in gem5 requires the introduction
of new miscReg flags as there are some EL2 registers which are
accessible from secure mode only

Change-Id: Ib1f0633ed23ea2364670d37c1fefd345ab2363ae
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37615
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2020-11-10 15:01:47 +00:00
parent 8351953016
commit 7ad2f0e519
3 changed files with 71 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

51
src/arch/arm/isa.hh
View File

@@ -252,12 +252,30 @@ namespace ArmISA
privNonSecureRead(v);
return *this;
}
chain hypE2HSecureRead(bool v = true) const {
info[MISCREG_HYP_E2H_S_RD] = v;
return *this;
}
chain hypE2HNonSecureRead(bool v = true) const {
info[MISCREG_HYP_E2H_NS_RD] = v;
return *this;
}
chain hypE2HRead(bool v = true) const {
info[MISCREG_HYP_E2H_RD] = v;
hypE2HSecureRead(v);
hypE2HNonSecureRead(v);
return *this;
}
chain hypE2HSecureWrite(bool v = true) const {
info[MISCREG_HYP_E2H_S_WR] = v;
return *this;
}
chain hypE2HNonSecureWrite(bool v = true) const {
info[MISCREG_HYP_E2H_NS_WR] = v;
return *this;
}
chain hypE2HWrite(bool v = true) const {
info[MISCREG_HYP_E2H_WR] = v;
hypE2HSecureWrite(v);
hypE2HNonSecureWrite(v);
return *this;
}
chain hypE2H(bool v = true) const {
@@ -265,14 +283,39 @@ namespace ArmISA
hypE2HWrite(v);
return *this;
}
chain hypSecureRead(bool v = true) const {
info[MISCREG_HYP_S_RD] = v;
return *this;
}
chain hypNonSecureRead(bool v = true) const {
info[MISCREG_HYP_NS_RD] = v;
return *this;
}
chain hypRead(bool v = true) const {
hypE2HRead(v);
info[MISCREG_HYP_RD] = v;
hypSecureRead(v);
hypNonSecureRead(v);
return *this;
}
chain hypSecureWrite(bool v = true) const {
info[MISCREG_HYP_S_WR] = v;
return *this;
}
chain hypNonSecureWrite(bool v = true) const {
info[MISCREG_HYP_NS_WR] = v;
return *this;
}
chain hypWrite(bool v = true) const {
hypE2HWrite(v);
info[MISCREG_HYP_WR] = v;
hypSecureWrite(v);
hypNonSecureWrite(v);
return *this;
}
chain hypSecure(bool v = true) const {
hypE2HSecureRead(v);
hypE2HSecureWrite(v);
hypSecureRead(v);
hypSecureWrite(v);
return *this;
}
chain hyp(bool v = true) const {

22
src/arch/arm/miscregs.cc
View File

@@ -1230,7 +1230,7 @@ canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
miscRegInfo[reg][MISCREG_MON_NS1_RD];
break;
case MODE_HYP:
canRead = miscRegInfo[reg][MISCREG_HYP_RD];
canRead = miscRegInfo[reg][MISCREG_HYP_NS_RD];
break;
default:
undefined = true;
@@ -1276,7 +1276,7 @@ canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
miscRegInfo[reg][MISCREG_MON_NS1_WR];
break;
case MODE_HYP:
canWrite = miscRegInfo[reg][MISCREG_HYP_WR];
canWrite = miscRegInfo[reg][MISCREG_HYP_NS_WR];
break;
default:
undefined = true;
@@ -1397,8 +1397,13 @@ canReadAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
miscRegInfo[reg][MISCREG_PRI_NS_RD];
case EL2:
return el2_host ? miscRegInfo[reg][MISCREG_HYP_E2H_RD] :
miscRegInfo[reg][MISCREG_HYP_RD];
if (el2_host) {
return secure ? miscRegInfo[reg][MISCREG_HYP_E2H_S_RD] :
miscRegInfo[reg][MISCREG_HYP_E2H_NS_RD];
} else {
return secure ? miscRegInfo[reg][MISCREG_HYP_S_RD] :
miscRegInfo[reg][MISCREG_HYP_NS_RD];
}
case EL3:
return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_RD] :
secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
@@ -1428,8 +1433,13 @@ canWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
miscRegInfo[reg][MISCREG_PRI_NS_WR];
case EL2:
return el2_host ? miscRegInfo[reg][MISCREG_HYP_E2H_WR] :
miscRegInfo[reg][MISCREG_HYP_WR];
if (el2_host) {
return secure ? miscRegInfo[reg][MISCREG_HYP_E2H_S_WR] :
miscRegInfo[reg][MISCREG_HYP_E2H_NS_WR];
} else {
return secure ? miscRegInfo[reg][MISCREG_HYP_S_WR] :
miscRegInfo[reg][MISCREG_HYP_NS_WR];
}
case EL3:
return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_WR] :
secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :

12
src/arch/arm/miscregs.hh
View File

@@ -1121,11 +1121,15 @@ namespace ArmISA
MISCREG_PRI_S_RD,
MISCREG_PRI_S_WR,
// Hypervisor mode
MISCREG_HYP_RD,
MISCREG_HYP_WR,
MISCREG_HYP_NS_RD,
MISCREG_HYP_NS_WR,
MISCREG_HYP_S_RD,
MISCREG_HYP_S_WR,
// Hypervisor mode, HCR_EL2.E2H == 1
MISCREG_HYP_E2H_RD,
MISCREG_HYP_E2H_WR,
MISCREG_HYP_E2H_NS_RD,
MISCREG_HYP_E2H_NS_WR,
MISCREG_HYP_E2H_S_RD,
MISCREG_HYP_E2H_S_WR,
// Monitor mode, SCR.NS == 0
MISCREG_MON_NS0_RD,
MISCREG_MON_NS0_WR,