stdlib: Incorporating multi-isa work to the stdlib

The main restriction with this design is it results in one ISA target
per board. The ISA is declared per core. To make the design simpler it's
assumed a Processor (a collection of cores) are all of the same ISA. As
each board has one processor, this also means a board is typically tied
to one ISA per simulation.

In order to remain backwards compatible and maintain the standard
library APIs, this patch adds a `--main-isa` parameter which will
determine what `gem5.runtime.get_runtime_isa` returns in cases where
mutliple ISAs are compiled in. When setting the ISA in a simulation (via
the Processor or Cores), the user may, as before, choose not to and, in
this case, the `gem5.runtime.get_runtime_isa` function is used.

The `gem5.runtime.get_runtime_isa` function is an intermediate step
which should be removed in future versions of gem5 (users should specify
precisely what ISA they want via configuration scripts). For this reason
it throws a warning when used and should not be heavily relied upon. It
is deprecated.

Change-Id: Ia76541bfa9a5a4b6b86401309281849b49dc724b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55423
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs/example/gem5_library/arm-hello.py

@@ -62,7 +62,7 @@ cache_hierarchy = NoCache()
 memory = SingleChannelDDR3_1600(size="32MB")
 
 # We use a simple Timing processor with one core.
-processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, num_cores=1)
+processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, isa=ISA.ARM, num_cores=1)
 
 # The gem5 library simble board which can be used to run simple SE-mode
 # simulations.

configs/example/gem5_library/riscv-fs.py

@@ -66,7 +66,9 @@ cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
 memory = SingleChannelDDR3_1600()
 
 # Setup a single core Processor.
-processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, num_cores=1)
+processor = SimpleProcessor(
+    cpu_type=CPUTypes.TIMING, isa=ISA.RISCV, num_cores=1
+)
 
 # Setup the board.
 board = RiscvBoard(

configs/example/gem5_library/riscv-ubuntu-run.py

@@ -79,6 +79,7 @@ memory = DualChannelDDR4_2400(size = "3GB")
 # Here we setup the processor. We use a simple processor.
 processor = SimpleProcessor(
     cpu_type=CPUTypes.TIMING,
+    isa=ISA.RISCV,
     num_cores=2,
 )
 

configs/example/gem5_library/x86-gapbs-benchmarks.py

@@ -147,6 +147,7 @@ memory = DualChannelDDR4_2400(size="3GB")
 processor = SimpleSwitchableProcessor(
     starting_core_type=CPUTypes.KVM,
     switch_core_type=CPUTypes.TIMING,
+    isa=ISA.X86,
     num_cores=2,
 )
 

configs/example/gem5_library/x86-npb-benchmarks.py

@@ -164,6 +164,7 @@ memory = DualChannelDDR4_2400(size = "3GB")
 processor = SimpleSwitchableProcessor(
     starting_core_type=CPUTypes.KVM,
     switch_core_type=CPUTypes.TIMING,
+    isa=ISA.X86,
     num_cores=2,
 )
 

configs/example/gem5_library/x86-parsec-benchmarks.py

@@ -137,6 +137,7 @@ memory = DualChannelDDR4_2400(size = "3GB")
 processor = SimpleSwitchableProcessor(
     starting_core_type=CPUTypes.KVM,
     switch_core_type=CPUTypes.TIMING,
+    isa=ISA.X86,
     num_cores=2,
 )
 

configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py

@@ -187,6 +187,7 @@ memory = DualChannelDDR4_2400(size = "3GB")
 processor = SimpleSwitchableProcessor(
     starting_core_type=CPUTypes.KVM,
     switch_core_type=CPUTypes.TIMING,
+    isa=ISA.X86,
     num_cores=2,
 )
 

configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py

@@ -193,6 +193,7 @@ memory = DualChannelDDR4_2400(size = "3GB")
 processor = SimpleSwitchableProcessor(
     starting_core_type=CPUTypes.KVM,
     switch_core_type=CPUTypes.TIMING,
+    isa=ISA.X86,
     num_cores=2,
 )
 

configs/example/gem5_library/x86-ubuntu-run-with-kvm.py

@@ -89,6 +89,7 @@ memory = SingleChannelDDR3_1600(size="3GB")
 processor = SimpleSwitchableProcessor(
     starting_core_type=CPUTypes.KVM,
     switch_core_type=CPUTypes.TIMING,
+    isa=ISA.X86,
     num_cores=2,
 )
 

configs/example/lupv/run_lupv.py

@@ -36,7 +36,6 @@ Characteristics
 import m5
 from m5.objects import Root
 
-from gem5.runtime import get_runtime_isa
 from gem5.components.boards.experimental.lupv_board import LupvBoard
 from gem5.components.memory.single_channel import SingleChannelDDR3_1600
 from gem5.components.processors.simple_processor import SimpleProcessor
@@ -83,11 +82,11 @@ memory = SingleChannelDDR3_1600(size="128MB")
 # Setup a single core Processor.
 if args.cpu_type == "atomic":
     processor = SimpleProcessor(
-        cpu_type=CPUTypes.ATOMIC, num_cores=args.num_cpus
+        cpu_type=CPUTypes.ATOMIC, num_cores=args.num_cpus, isa=ISA.RISCV
     )
 elif args.cpu_type == "timing":
     processor = SimpleProcessor(
-        cpu_type=CPUTypes.TIMING, num_cores=args.num_cpus
+        cpu_type=CPUTypes.TIMING, num_cores=args.num_cpus, isa=ISA.RISCV
     )
 
 # Setup the board.
@@ -106,7 +105,7 @@ board.set_kernel_disk_workload(
 
 
 # Begin running of the simulation.
-print("Running with ISA: " + get_runtime_isa().name)
+print("Running with ISA: " + processor.get_isa().name)
 print()
 root = Root(full_system=True, system=board)
 m5.instantiate()