The main restriction with this design is it results in one ISA target per board. The ISA is declared per core. To make the design simpler it's assumed a Processor (a collection of cores) are all of the same ISA. As each board has one processor, this also means a board is typically tied to one ISA per simulation. In order to remain backwards compatible and maintain the standard library APIs, this patch adds a `--main-isa` parameter which will determine what `gem5.runtime.get_runtime_isa` returns in cases where mutliple ISAs are compiled in. When setting the ISA in a simulation (via the Processor or Cores), the user may, as before, choose not to and, in this case, the `gem5.runtime.get_runtime_isa` function is used. The `gem5.runtime.get_runtime_isa` function is an intermediate step which should be removed in future versions of gem5 (users should specify precisely what ISA they want via configuration scripts). For this reason it throws a warning when used and should not be heavily relied upon. It is deprecated. Change-Id: Ia76541bfa9a5a4b6b86401309281849b49dc724b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55423 Reviewed-by: Gabe Black <gabe.black@gmail.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
297 lines
9.1 KiB
Python
297 lines
9.1 KiB
Python
# Copyright (c) 2021 The Regents of the University of California.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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"""
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Script to run PARSEC benchmarks with gem5.
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The script expects a benchmark program name and the simulation
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size. The system is fixed with 2 CPU cores, MESI Two Level system
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cache and 3 GB DDR4 memory. It uses the x86 board.
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This script will count the total number of instructions executed
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in the ROI. It also tracks how much wallclock and simulated time.
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Usage:
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------
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```
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scons build/X86/gem5.opt
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./build/X86/gem5.opt \
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configs/example/gem5_library/x86-parsec-benchmarks.py \
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--benchmark <benchmark_name> \
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--size <simulation_size>
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```
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"""
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import argparse
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import time
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import m5
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from m5.objects import Root
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from gem5.utils.requires import requires
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from gem5.components.boards.x86_board import X86Board
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from gem5.components.memory import DualChannelDDR4_2400
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from gem5.components.processors.simple_switchable_processor import(
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SimpleSwitchableProcessor,
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)
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from gem5.components.processors.cpu_types import CPUTypes
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from gem5.isas import ISA
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from gem5.coherence_protocol import CoherenceProtocol
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from gem5.resources.resource import Resource
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from m5.stats.gem5stats import get_simstat
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# We check for the required gem5 build.
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requires(
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isa_required = ISA.X86,
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coherence_protocol_required=CoherenceProtocol.MESI_TWO_LEVEL,
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kvm_required=True,
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)
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# Following are the list of benchmark programs for parsec.
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benchmark_choices = ["blackscholes", "bodytrack", "canneal", "dedup",
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"facesim", "ferret", "fluidanimate", "freqmine",
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"raytrace", "streamcluster", "swaptions", "vips", "x264"]
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# Following are the input size.
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size_choices=["simsmall", "simmedium", "simlarge"]
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parser = argparse.ArgumentParser(
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description="An example configuration script to run the npb benchmarks."
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)
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# The arguments accepted are the benchmark name and the simulation size.
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parser.add_argument(
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"--benchmark",
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type = str,
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required=True,
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help = "Input the benchmark program to execute.",
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choices = benchmark_choices,
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)
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parser.add_argument(
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"--size",
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type = str,
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required=True,
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help = "Simulation size the benchmark program.",
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choices = size_choices,
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)
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args = parser.parse_args()
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# Setting up all the fixed system parameters here
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# Caches: MESI Two Level Cache Hierarchy
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from gem5.components.cachehierarchies.ruby.\
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mesi_two_level_cache_hierarchy import(
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MESITwoLevelCacheHierarchy,
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)
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cache_hierarchy = MESITwoLevelCacheHierarchy(
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l1d_size = "32kB",
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l1d_assoc = 8,
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l1i_size="32kB",
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l1i_assoc=8,
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l2_size="256kB",
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l2_assoc=16,
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num_l2_banks=2,
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)
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# Memory: Dual Channel DDR4 2400 DRAM device.
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# The X86 board only supports 3 GB of main memory.
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memory = DualChannelDDR4_2400(size = "3GB")
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# Here we setup the processor. This is a special switchable processor in which
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# a starting core type and a switch core type must be specified. Once a
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# configuration is instantiated a user may call `processor.switch()` to switch
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# from the starting core types to the switch core types. In this simulation
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# we start with KVM cores to simulate the OS boot, then switch to the Timing
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# cores for the command we wish to run after boot.
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processor = SimpleSwitchableProcessor(
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starting_core_type=CPUTypes.KVM,
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switch_core_type=CPUTypes.TIMING,
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isa=ISA.X86,
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num_cores=2,
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)
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# Here we setup the board. The X86Board allows for Full-System X86 simulations
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board = X86Board(
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clk_freq="3GHz",
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processor=processor,
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memory=memory,
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cache_hierarchy=cache_hierarchy,
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)
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# Here we set the FS workload, i.e., parsec benchmark
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# After simulation has ended you may inspect
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# `m5out/system.pc.com_1.device` to the stdout, if any.
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# After the system boots, we execute the benchmark program and wait till the
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# ROI `workbegin` annotation is reached (m5_work_begin()). We start collecting
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# the number of committed instructions till ROI ends (marked by `workend`).
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# We then finish executing the rest of the benchmark.
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# Also, we sleep the system for some time so that the output is printed
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# properly.
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command = "cd /home/gem5/parsec-benchmark;".format(args.benchmark) \
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+ "source env.sh;" \
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+ "parsecmgmt -a run -p {} -c gcc-hooks -i {} \
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-n {};".format(args.benchmark, args.size, "2") \
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+ "sleep 5;" \
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+ "m5 exit;" \
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board.set_kernel_disk_workload(
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# The x86 linux kernel will be automatically downloaded to the
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# `~/.cache/gem5` directory if not already present.
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# PARSEC benchamarks were tested with kernel version 4.19.83
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kernel=Resource(
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"x86-linux-kernel-4.19.83",
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),
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# The x86-parsec image will be automatically downloaded to the
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# `~/.cache/gem5` directory if not already present.
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disk_image=Resource(
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"x86-parsec",
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),
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readfile_contents=command,
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)
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# We need this for long running processes.
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m5.disableAllListeners()
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root = Root(full_system = True, system = board)
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# sim_quantum must be set if KVM cores are used.
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root.sim_quantum = int(1e9)
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m5.instantiate()
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# We maintain the wall clock time.
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globalStart = time.time()
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print("Running the simulation")
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print("Using KVM cpu")
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start_tick = m5.curTick()
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end_tick = m5.curTick()
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m5.stats.reset()
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# We start the simulation
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exit_event = m5.simulate()
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# The first exit_event ends with a `workbegin` cause. This means that the
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# system booted successfully and the execution on the program started.
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if exit_event.getCause() == "workbegin":
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print("Done booting Linux")
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print("Resetting stats at the start of ROI!")
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m5.stats.reset()
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start_tick = m5.curTick()
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# We have completed up to this step using KVM cpu. Now we switch to timing
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# cpu for detailed simulation.
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processor.switch()
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else:
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# `workbegin` call was never encountered.
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print("Unexpected termination of simulation before ROI was reached!")
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print(
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"Exiting @ tick {} because {}.".format(
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m5.curTick(),
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exit_event.getCause()
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)
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)
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exit(-1)
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# The next exit_event is to simulate the ROI. It should be exited with a cause
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# marked by `workend`.
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exit_event = m5.simulate()
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# Reached the end of ROI.
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# We dump the stats here.
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# We exepect that ROI ends with `workend`. Otherwise the simulation ended
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# unexpectedly.
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if exit_event.getCause() == "workend":
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print("Dump stats at the end of the ROI!")
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m5.stats.dump()
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end_tick = m5.curTick()
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else:
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print("Unexpected termination of simulation while ROI was being executed!")
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print(
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"Exiting @ tick {} because {}.".format(
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m5.curTick(),
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exit_event.getCause()
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)
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)
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exit(-1)
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# ROI has ended here, and we get `simInsts` using get_simstat and print it in
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# the final print statement.
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gem5stats = get_simstat(root)
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# We get the number of committed instructions from the timing
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# cores. We then sum and print them at the end.
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roi_insts = float(\
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gem5stats.to_json()\
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["system"]["processor"]["cores2"]["core"]["exec_context.thread_0"]\
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["numInsts"]["value"]) + float(\
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gem5stats.to_json()\
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["system"]["processor"]["cores3"]["core"]["exec_context.thread_0"]\
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["numInsts"]["value"]\
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)
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# Simulation is over at this point. We acknowledge that all the simulation
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# events were successful.
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print("All simulation events were successful.")
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# We print the final simulation statistics.
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print("Done with the simulation")
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print()
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print("Performance statistics:")
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print("Simulated time in ROI: %.2fs" % ((end_tick-start_tick)/1e12))
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print("Instructions executed in ROI: %d" % ((roi_insts)))
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print("Ran a total of", m5.curTick()/1e12, "simulated seconds")
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print("Total wallclock time: %.2fs, %.2f min" % \
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(time.time()-globalStart, (time.time()-globalStart)/60))
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