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ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR.

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Gabe Black
2009-11-08 01:59:20 -08:00
parent f63c260d89
commit 78bd8fe44f
2 changed files with 5 additions and 3 deletions
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2
src/arch/arm/intregs.hh
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@@ -102,6 +102,8 @@ enum IntRegIndex
INTREG_ZERO, // Dummy zero reg since there has to be one.
INTREG_UREG0,
INTREG_RHI,
INTREG_RLO,
NUM_INTREGS,
NUM_ARCH_INTREGS = INTREG_PC + 1,

6
src/arch/arm/isa/operands.isa
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@@ -63,9 +63,9 @@ def operands {{
'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 7),
'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 8),
'LR': ('IntReg', 'uw', '14', 'IsInteger', 9),
'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7),
'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8),
'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
#Register fields for microops
'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),