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arch-arm: Add used attribute to pauth_helpers asserts

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Adding M5_VAR_USED attribute to variables in pauth_helpers so that
gem5.fast builds.

Change-Id: I45dd70ea2e921f7ce68ea52147abdd40da99f37e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25364
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Matthew Poremba
2020-02-12 14:07:43 -08:00
parent 015eeec1f4
commit 789eb0fb8f
1 changed files with 2 additions and 3 deletions
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5
src/arch/arm/pauth_helpers.cc
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@@ -113,9 +113,8 @@ ArmISA::calculateBottomPACBit(ThreadContext* tc, ExceptionLevel el,
Fault
ArmISA::trapPACUse(ThreadContext *tc, ExceptionLevel target_el)
{
ExceptionLevel curr_el = currEL(tc);
assert(ArmSystem::haveEL(tc, target_el) &&
target_el != EL0 && (target_el >= curr_el));
target_el != EL0 && (target_el >= currEL(tc)));
switch (target_el) {
case EL2:
@@ -149,7 +148,7 @@ ArmISA::addPAC (ThreadContext* tc, ExceptionLevel el, uint64_t ptr,
if (upperAndLowerRange(tc, el)) {
ExceptionLevel s1_el = s1TranslationRegime(tc, el);
assert (s1_el == EL1 || s1_el == EL2);
if (s1TranslationRegime(tc, el) == EL1) {
if (s1_el == EL1) {
// EL1 translation regime registers
TCR tcr = tc->readMiscReg(MISCREG_TCR_EL1);
if (data) {