arch-riscv,configs,python: Update riscv_fs.py/riscv_board.py
This patch incoporates improvements to the riscv_fs.py and riscv_board.py: * Adds 'Resource' objects to download needed resources. * Adds 'requires' function calls where necessary. Change-Id: I2ae4f34221d781ed6d71c9f69d56833845f537c4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49867 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
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@@ -33,6 +33,8 @@ Characteristics
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* Runs exclusively on the RISC-V ISA with the classic caches
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* Assumes that the kernel is compiled into the bootloader
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* Automatically generates the DTB file
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* Will boot but requires a user to login using `m5term` (username: `root`,
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password: `root`)
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"""
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import m5
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@@ -44,21 +46,16 @@ from gem5.components.memory.single_channel import SingleChannelDDR3_1600
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from gem5.components.processors.simple_processor import SimpleProcessor
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from gem5.components.processors.cpu_types import CPUTypes
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from gem5.isas import ISA
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import os
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import subprocess
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import gzip
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import shutil
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from gem5.utils.requires import requires
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from gem5.resources.resource import Resource
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# Run a check to ensure the right version of gem5 is being used.
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if get_runtime_isa() != ISA.RISCV:
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raise EnvironmentError("The riscv_fs.py should be run with RISCV ISA.")
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requires(isa_required=ISA.RISCV)
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from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy \
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import (
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PrivateL1PrivateL2CacheHierarchy,
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)
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from gem5.boards.riscv_board import RiscvBoard
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# Setup the cache hierarchy. PrivateL1PrivateL2 and NoCache have been tested.
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cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
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@@ -81,43 +78,19 @@ board = RiscvBoard(
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board.connect_things()
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# Download the resources as necessary.
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thispath = os.path.dirname(os.path.realpath(__file__))
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bootloader_url = (
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"http://dist.gem5.org/dist/develop/kernels/"
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"riscv/static/bootloader-vmlinux-5.10"
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)
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bootloader_path = os.path.join(thispath, "bootloader-vmlinux-5.10")
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if not os.path.exists(bootloader_path):
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subprocess.run(["wget", "-P", thispath, bootloader_url])
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boot_img_url = (
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"http://dist.gem5.org/dist/develop/images/riscv/busybox/riscv-disk.img.gz"
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)
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boot_img_path_gz = os.path.join(thispath, "riscv-disk.img.gz")
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boot_img_path = os.path.join(thispath, "riscv-disk.img")
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if not os.path.exists(boot_img_path):
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subprocess.run(["wget", "-P", thispath, boot_img_url])
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with gzip.open(boot_img_path_gz, "rb") as f:
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with open(boot_img_path, "wb") as o:
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shutil.copyfileobj(f, o)
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# Set the Full System workload.
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board.set_workload(disk_image=boot_img_path, bootloader=bootloader_path)
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# Begin running of the simulation. This will exit once the Linux system boot
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# is complete.
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print("Running with ISA: " + get_runtime_isa().name)
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print()
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board.set_workload(disk_image=Resource("riscv-disk-img"),
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bootloader=Resource("riscv-bootloader-vmlinux-5.10"))
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root = Root(full_system=True, system=board)
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m5.instantiate()
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print("Beginning simulation!")
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# Note: This simulation will never stop. You can access the terminal upon boot
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# using m5term (`./util/term`): `./m5term localhost <port>`. Note the `<port>`
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# value is obtained from the gem5 terminal stdout. Look out for
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# "system.platform.terminal: Listening for connections on port <port>".
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exit_event = m5.simulate()
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print(
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"Exiting @ tick {} because {}.".format(m5.curTick(), exit_event.getCause())
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@@ -33,8 +33,10 @@ from .abstract_board import AbstractBoard
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from ..processors.abstract_processor import AbstractProcessor
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from ..memory.abstract_memory_system import AbstractMemorySystem
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from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy
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from ...resources.resource import AbstractResource
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from ...isas import ISA
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from ...runtime import get_runtime_isa
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from ...utils.requires import requires
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import m5
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@@ -85,11 +87,8 @@ class RiscvBoard(SimpleBoard):
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) -> None:
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super().__init__(clk_freq, processor, memory, cache_hierarchy)
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if get_runtime_isa() != ISA.RISCV:
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raise EnvironmentError(
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"RiscvBoard will only work with the RISC-V ISA. Please"
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" recompile gem5 with ISA=RISCV."
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)
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requires(isa_required=ISA.RISCV)
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if cache_hierarchy.is_ruby():
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raise EnvironmentError("RiscvBoard is not compatible with Ruby")
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@@ -176,8 +175,9 @@ class RiscvBoard(SimpleBoard):
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memory.set_memory_range(self.mem_ranges)
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def set_workload(
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self, bootloader: str, disk_image: str, command: Optional[str] = None
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):
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self, bootloader: AbstractResource, disk_image: AbstractResource,
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command: Optional[str] = None
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) -> None:
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"""Setup the full system files
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See http://resources.gem5.org/resources/riscv-fs for the currently
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@@ -195,18 +195,19 @@ class RiscvBoard(SimpleBoard):
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* Disk must be configured correctly to use the command option
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* This board doesn't support the command option
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:param bootloader: The compiled bootloader with the kernel as a payload
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:param disk_image: A disk image containing the OS data. The first
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partition should be the root partition.
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:param bootloader: The resource encapsulating the compiled bootloader
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with the kernel as a payload
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:param disk_image: The resource encapsulating the disk image containing
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the OS data. The first partition should be the root partition.
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:param command: The command(s) to run with bash once the OS is booted
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"""
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self.workload.object_file = bootloader
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self.workload.object_file = bootloader.get_local_path()
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image = CowDiskImage(
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child=RawDiskImage(read_only=True), read_only=False
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)
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image.child.image_file = disk_image
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image.child.image_file = disk_image.get_local_path()
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self.disk.vio.image = image
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self.workload.command_line = "console=ttyS0 root=/dev/vda ro"
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