configs: Instantiate RNFs and MN via callbacks
This commit allows top level configs making use of the Ruby module to define node generation callbacks. The config_ruby function will check the system object for two factory methods 1) _rnf_gen, if defined, will be called to generate RNFs 2) _mn_gen, if defined, will be called to generate MNs Change-Id: I9daeece646e7cdb2d3bfefa761a9650562f8eb4b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
committed by
Bobby R. Bruce
parent
390c2b67e4
commit
76541929c9
@@ -1,4 +1,4 @@
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# Copyright (c) 2021 ARM Limited
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# Copyright (c) 2021, 2024 Arm Limited
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# All rights reserved.
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# All rights reserved.
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#
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#
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# The license below extends only to copyright in the software and shall
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# The license below extends only to copyright in the software and shall
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@@ -102,32 +102,6 @@ def create_system(
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CHI_RNI_DMA = chi_defs.CHI_RNI_DMA
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CHI_RNI_DMA = chi_defs.CHI_RNI_DMA
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CHI_RNI_IO = chi_defs.CHI_RNI_IO
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CHI_RNI_IO = chi_defs.CHI_RNI_IO
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# Declare caches and controller types used by the protocol
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# Notice tag and data accesses are not concurrent, so the a cache hit
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# latency = tag + data + response latencies.
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# Default response latencies are 1 cy for all controllers.
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# For L1 controllers the mandatoryQueue enqueue latency is always 1 cy and
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# this is deducted from the initial tag read latency for sequencer requests
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# dataAccessLatency may be set to 0 if one wants to consider parallel
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# data and tag lookups
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class L1ICache(RubyCache):
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dataAccessLatency = 1
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tagAccessLatency = 1
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size = options.l1i_size
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assoc = options.l1i_assoc
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class L1DCache(RubyCache):
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dataAccessLatency = 2
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tagAccessLatency = 1
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size = options.l1d_size
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assoc = options.l1d_assoc
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class L2Cache(RubyCache):
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dataAccessLatency = 6
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tagAccessLatency = 2
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size = options.l2_size
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assoc = options.l2_assoc
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class HNFCache(RubyCache):
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class HNFCache(RubyCache):
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dataAccessLatency = 10
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dataAccessLatency = 10
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tagAccessLatency = 2
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tagAccessLatency = 2
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@@ -147,25 +121,23 @@ def create_system(
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# Creates on RNF per cpu with priv l2 caches
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# Creates on RNF per cpu with priv l2 caches
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assert len(cpus) == options.num_cpus
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assert len(cpus) == options.num_cpus
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ruby_system.rnf = [
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CHI_RNF(
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rnf_cb = getattr(system, "_rnf_gen", CHI_RNF.generate)
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[cpu],
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ruby_system,
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# Generate the Request Nodes
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L1ICache,
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ruby_system.rnf = rnf_cb(options, ruby_system, cpus)
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L1DCache,
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system.cache_line_size.value,
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)
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for cpu in cpus
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]
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for rnf in ruby_system.rnf:
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for rnf in ruby_system.rnf:
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rnf.addPrivL2Cache(L2Cache)
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cpu_sequencers.extend(rnf.getSequencers())
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cpu_sequencers.extend(rnf.getSequencers())
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all_cntrls.extend(rnf.getAllControllers())
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all_cntrls.extend(rnf.getAllControllers())
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network_nodes.append(rnf)
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network_nodes.append(rnf)
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network_cntrls.extend(rnf.getNetworkSideControllers())
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network_cntrls.extend(rnf.getNetworkSideControllers())
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# Creates one Misc Node
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mn_cb = getattr(system, "_mn_gen", CHI_MN.generate)
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ruby_system.mn = [CHI_MN(ruby_system, [cpu.l1d for cpu in cpus])]
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# Generate the Misc Nodes
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ruby_system.mn = mn_cb(options, ruby_system, cpus)
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for mn in ruby_system.mn:
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for mn in ruby_system.mn:
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all_cntrls.extend(mn.getAllControllers())
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all_cntrls.extend(mn.getAllControllers())
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network_nodes.append(mn)
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network_nodes.append(mn)
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@@ -1,4 +1,4 @@
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# Copyright (c) 2021-2023 ARM Limited
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# Copyright (c) 2021-2024 Arm Limited
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# All rights reserved.
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# All rights reserved.
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#
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#
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# The license below extends only to copyright in the software and shall
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# The license below extends only to copyright in the software and shall
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@@ -51,6 +51,29 @@ import m5
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from m5.objects import *
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from m5.objects import *
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# Declare caches and controller types used by the protocol
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# Notice tag and data accesses are not concurrent, so the a cache hit
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# latency = tag + data + response latencies.
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# Default response latencies are 1 cy for all controllers.
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# For L1 controllers the mandatoryQueue enqueue latency is always 1 cy and
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# this is deducted from the initial tag read latency for sequencer requests
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# dataAccessLatency may be set to 0 if one wants to consider parallel
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# data and tag lookups
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class L1ICache(RubyCache):
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dataAccessLatency = 1
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tagAccessLatency = 1
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class L1DCache(RubyCache):
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dataAccessLatency = 2
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tagAccessLatency = 1
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class L2Cache(RubyCache):
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dataAccessLatency = 6
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tagAccessLatency = 2
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class Versions:
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class Versions:
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"""
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"""
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Helper class to obtain unique ids for a given controller class.
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Helper class to obtain unique ids for a given controller class.
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@@ -575,6 +598,24 @@ class CHI_RNF(CHI_Node):
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c.downstream_destinations = [cpu.l2]
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c.downstream_destinations = [cpu.l2]
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cpu._ll_cntrls = [cpu.l2]
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cpu._ll_cntrls = [cpu.l2]
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@classmethod
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def generate(cls, options, ruby_system, cpus):
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rnfs = [
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CHI_RNF(
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[cpu],
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ruby_system,
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L1ICache(size=options.l1i_size, assoc=options.l1i_assoc),
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L1DCache(size=options.l1d_size, assoc=options.l1d_assoc),
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options.cacheline_size,
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)
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for cpu in cpus
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]
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for rnf in rnfs:
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rnf.addPrivL2Cache(
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L2Cache(size=options.l2_size, assoc=options.l2_assoc)
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)
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return rnfs
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class CHI_HNF(CHI_Node):
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class CHI_HNF(CHI_Node):
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"""
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"""
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@@ -678,6 +719,13 @@ class CHI_MN(CHI_Node):
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def getNetworkSideControllers(self):
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def getNetworkSideControllers(self):
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return [self._cntrl]
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return [self._cntrl]
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@classmethod
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def generate(cls, options, ruby_system, cpus):
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"""
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Creates one Misc Node
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"""
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return [CHI_MN(ruby_system, [cpu.l1d for cpu in cpus])]
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class CHI_SNF_Base(CHI_Node):
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class CHI_SNF_Base(CHI_Node):
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"""
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"""
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