configs: Instantiate RNFs and MN via callbacks

This commit allows top level configs making use of the Ruby module
to define node generation callbacks.
The config_ruby function will check the system object for two
factory methods

1) _rnf_gen, if defined, will be called to generate RNFs
2) _mn_gen, if defined, will be called to generate MNs

Change-Id: I9daeece646e7cdb2d3bfefa761a9650562f8eb4b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Giacomo Travaglini
2023-07-05 14:50:18 +01:00
committed by Bobby R. Bruce
parent 390c2b67e4
commit 76541929c9
2 changed files with 61 additions and 41 deletions

View File

@@ -1,4 +1,4 @@
# Copyright (c) 2021 ARM Limited # Copyright (c) 2021, 2024 Arm Limited
# All rights reserved. # All rights reserved.
# #
# The license below extends only to copyright in the software and shall # The license below extends only to copyright in the software and shall
@@ -102,32 +102,6 @@ def create_system(
CHI_RNI_DMA = chi_defs.CHI_RNI_DMA CHI_RNI_DMA = chi_defs.CHI_RNI_DMA
CHI_RNI_IO = chi_defs.CHI_RNI_IO CHI_RNI_IO = chi_defs.CHI_RNI_IO
# Declare caches and controller types used by the protocol
# Notice tag and data accesses are not concurrent, so the a cache hit
# latency = tag + data + response latencies.
# Default response latencies are 1 cy for all controllers.
# For L1 controllers the mandatoryQueue enqueue latency is always 1 cy and
# this is deducted from the initial tag read latency for sequencer requests
# dataAccessLatency may be set to 0 if one wants to consider parallel
# data and tag lookups
class L1ICache(RubyCache):
dataAccessLatency = 1
tagAccessLatency = 1
size = options.l1i_size
assoc = options.l1i_assoc
class L1DCache(RubyCache):
dataAccessLatency = 2
tagAccessLatency = 1
size = options.l1d_size
assoc = options.l1d_assoc
class L2Cache(RubyCache):
dataAccessLatency = 6
tagAccessLatency = 2
size = options.l2_size
assoc = options.l2_assoc
class HNFCache(RubyCache): class HNFCache(RubyCache):
dataAccessLatency = 10 dataAccessLatency = 10
tagAccessLatency = 2 tagAccessLatency = 2
@@ -147,25 +121,23 @@ def create_system(
# Creates on RNF per cpu with priv l2 caches # Creates on RNF per cpu with priv l2 caches
assert len(cpus) == options.num_cpus assert len(cpus) == options.num_cpus
ruby_system.rnf = [
CHI_RNF( rnf_cb = getattr(system, "_rnf_gen", CHI_RNF.generate)
[cpu],
ruby_system, # Generate the Request Nodes
L1ICache, ruby_system.rnf = rnf_cb(options, ruby_system, cpus)
L1DCache,
system.cache_line_size.value,
)
for cpu in cpus
]
for rnf in ruby_system.rnf: for rnf in ruby_system.rnf:
rnf.addPrivL2Cache(L2Cache)
cpu_sequencers.extend(rnf.getSequencers()) cpu_sequencers.extend(rnf.getSequencers())
all_cntrls.extend(rnf.getAllControllers()) all_cntrls.extend(rnf.getAllControllers())
network_nodes.append(rnf) network_nodes.append(rnf)
network_cntrls.extend(rnf.getNetworkSideControllers()) network_cntrls.extend(rnf.getNetworkSideControllers())
# Creates one Misc Node mn_cb = getattr(system, "_mn_gen", CHI_MN.generate)
ruby_system.mn = [CHI_MN(ruby_system, [cpu.l1d for cpu in cpus])]
# Generate the Misc Nodes
ruby_system.mn = mn_cb(options, ruby_system, cpus)
for mn in ruby_system.mn: for mn in ruby_system.mn:
all_cntrls.extend(mn.getAllControllers()) all_cntrls.extend(mn.getAllControllers())
network_nodes.append(mn) network_nodes.append(mn)

View File

@@ -1,4 +1,4 @@
# Copyright (c) 2021-2023 ARM Limited # Copyright (c) 2021-2024 Arm Limited
# All rights reserved. # All rights reserved.
# #
# The license below extends only to copyright in the software and shall # The license below extends only to copyright in the software and shall
@@ -51,6 +51,29 @@ import m5
from m5.objects import * from m5.objects import *
# Declare caches and controller types used by the protocol
# Notice tag and data accesses are not concurrent, so the a cache hit
# latency = tag + data + response latencies.
# Default response latencies are 1 cy for all controllers.
# For L1 controllers the mandatoryQueue enqueue latency is always 1 cy and
# this is deducted from the initial tag read latency for sequencer requests
# dataAccessLatency may be set to 0 if one wants to consider parallel
# data and tag lookups
class L1ICache(RubyCache):
dataAccessLatency = 1
tagAccessLatency = 1
class L1DCache(RubyCache):
dataAccessLatency = 2
tagAccessLatency = 1
class L2Cache(RubyCache):
dataAccessLatency = 6
tagAccessLatency = 2
class Versions: class Versions:
""" """
Helper class to obtain unique ids for a given controller class. Helper class to obtain unique ids for a given controller class.
@@ -575,6 +598,24 @@ class CHI_RNF(CHI_Node):
c.downstream_destinations = [cpu.l2] c.downstream_destinations = [cpu.l2]
cpu._ll_cntrls = [cpu.l2] cpu._ll_cntrls = [cpu.l2]
@classmethod
def generate(cls, options, ruby_system, cpus):
rnfs = [
CHI_RNF(
[cpu],
ruby_system,
L1ICache(size=options.l1i_size, assoc=options.l1i_assoc),
L1DCache(size=options.l1d_size, assoc=options.l1d_assoc),
options.cacheline_size,
)
for cpu in cpus
]
for rnf in rnfs:
rnf.addPrivL2Cache(
L2Cache(size=options.l2_size, assoc=options.l2_assoc)
)
return rnfs
class CHI_HNF(CHI_Node): class CHI_HNF(CHI_Node):
""" """
@@ -678,6 +719,13 @@ class CHI_MN(CHI_Node):
def getNetworkSideControllers(self): def getNetworkSideControllers(self):
return [self._cntrl] return [self._cntrl]
@classmethod
def generate(cls, options, ruby_system, cpus):
"""
Creates one Misc Node
"""
return [CHI_MN(ruby_system, [cpu.l1d for cpu in cpus])]
class CHI_SNF_Base(CHI_Node): class CHI_SNF_Base(CHI_Node):
""" """