mem-ruby: Implement a CHI generic controller
Component implementing a generic controller that allow classic caches interaction with Ruby/CHI. The CHIGenericController provides an interface to send/receive CHI messages to/from the interconnect. This is implement in C++ rather then SLICC. This controller is seen as a MachineType:Cache by the CHI implementation in SLICC. Change-Id: I3afc4363f4290095c2f7428c8487bccd932e0300
This commit is contained in:
Tiago Mück
committed by
Bobby R. Bruce
Bobby R. Bruce
parent
488c6fc246
commit
390c2b67e4
55
src/mem/ruby/protocol/chi/generic/CHIGeneric.py
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55
src/mem/ruby/protocol/chi/generic/CHIGeneric.py
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@@ -0,0 +1,55 @@
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# Copyright (c) 2023 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
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# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.objects.Controller import RubyController
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from m5.params import *
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class CHIGenericController(RubyController):
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type = "CHIGenericController"
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cxx_header = "mem/ruby/protocol/chi/generic/CHIGenericController.hh"
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cxx_class = "gem5::ruby::CHIGenericController"
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abstract = True
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data_channel_size = Param.Int("")
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reqOut = Param.MessageBuffer("")
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snpOut = Param.MessageBuffer("")
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rspOut = Param.MessageBuffer("")
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datOut = Param.MessageBuffer("")
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reqIn = Param.MessageBuffer("")
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snpIn = Param.MessageBuffer("")
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rspIn = Param.MessageBuffer("")
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datIn = Param.MessageBuffer("")
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290
src/mem/ruby/protocol/chi/generic/CHIGenericController.cc
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290
src/mem/ruby/protocol/chi/generic/CHIGenericController.cc
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@@ -0,0 +1,290 @@
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/*
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* Copyright (c) 2023 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
|
||||
* property including but not limited to intellectual property relating
|
||||
* to a hardware implementation of the functionality of the software
|
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* licensed hereunder. You may use the software subject to the license
|
||||
* terms below provided that you ensure that this notice is replicated
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||||
* unmodified and in its entirety in all distributions of the software,
|
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* modified or unmodified, in source code or in binary form.
|
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "mem/ruby/protocol/chi/generic/CHIGenericController.hh"
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#include <sys/types.h>
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#include <unistd.h>
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#include <cassert>
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#include <sstream>
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#include <string>
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#include <typeinfo>
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#include "debug/RubyCHIGeneric.hh"
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#include "mem/ruby/network/Network.hh"
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#include "mem/ruby/protocol/MemoryMsg.hh"
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#include "mem/ruby/system/RubySystem.hh"
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#include "mem/ruby/system/Sequencer.hh"
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namespace gem5
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{
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namespace ruby
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{
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CHIGenericController::CHIGenericController(const Params &p)
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: AbstractController(p),
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reqOut(p.reqOut), snpOut(p.snpOut),
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rspOut(p.rspOut), datOut(p.datOut),
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reqIn(p.reqIn), snpIn(p.snpIn),
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rspIn(p.rspIn), datIn(p.datIn),
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cacheLineSize(p.ruby_system->getBlockSizeBytes()),
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cacheLineBits(floorLog2(cacheLineSize)),
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dataChannelSize(p.data_channel_size),
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dataMsgsPerLine(cacheLineSize / p.data_channel_size)
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{
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m_machineID.type = MachineType_Cache;
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m_machineID.num = m_version;
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p.ruby_system->registerAbstractController(this);
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p.ruby_system->m_num_controllers[m_machineID.type]++;
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m_ruby_system = p.ruby_system;
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}
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void
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CHIGenericController::initNetQueues()
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{
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int base = m_ruby_system->MachineType_base_number(m_machineID.type);
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assert(m_net_ptr != nullptr);
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m_net_ptr->setToNetQueue(m_version + base, reqOut->getOrdered(),
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CHI_REQ, "none", reqOut);
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m_net_ptr->setToNetQueue(m_version + base, snpOut->getOrdered(),
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CHI_SNP, "none", snpOut);
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m_net_ptr->setToNetQueue(m_version + base, rspOut->getOrdered(),
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CHI_RSP, "none", rspOut);
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m_net_ptr->setToNetQueue(m_version + base, datOut->getOrdered(),
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CHI_DAT, "response", datOut);
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m_net_ptr->setFromNetQueue(m_version + base, reqIn->getOrdered(),
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CHI_REQ, "none", reqIn);
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m_net_ptr->setFromNetQueue(m_version + base, snpIn->getOrdered(),
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CHI_SNP, "none", snpIn);
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m_net_ptr->setFromNetQueue(m_version + base, rspIn->getOrdered(),
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CHI_RSP, "none", rspIn);
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m_net_ptr->setFromNetQueue(m_version + base, datIn->getOrdered(),
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CHI_DAT, "response", datIn);
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}
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void
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CHIGenericController::init()
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{
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AbstractController::init();
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rspIn->setConsumer(this);
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datIn->setConsumer(this);
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snpIn->setConsumer(this);
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reqIn->setConsumer(this);
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resetStats();
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}
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void
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CHIGenericController::addSequencer(RubyPort *seq)
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{
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assert(seq != nullptr);
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sequencers.emplace_back(seq);
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}
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void
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CHIGenericController::print(std::ostream& out) const
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{
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out << "[CHIGenericController " << m_version << "]";
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}
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Sequencer*
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CHIGenericController::getCPUSequencer() const
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{
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// CHIGenericController doesn't have a CPUSequencer
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return nullptr;
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}
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DMASequencer*
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CHIGenericController::getDMASequencer() const
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{
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// CHIGenericController doesn't have a DMASequencer
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return nullptr;
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}
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GPUCoalescer*
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CHIGenericController::getGPUCoalescer() const
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{
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// CHIGenericController doesn't have a GPUCoalescer
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return nullptr;
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}
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MessageBuffer*
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CHIGenericController::getMandatoryQueue() const
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{
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// CHIGenericController doesn't have a MandatoryQueue
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return nullptr;
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}
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MessageBuffer*
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CHIGenericController::getMemReqQueue() const
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{
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// CHIGenericController doesn't have a MemReqQueue
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return nullptr;
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}
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MessageBuffer*
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CHIGenericController::getMemRespQueue() const
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{
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// CHIGenericController doesn't have a MemRespQueue
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return nullptr;
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}
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void
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CHIGenericController::regStats()
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{
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AbstractController::regStats();
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}
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void
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CHIGenericController::collateStats()
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{
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}
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void
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CHIGenericController::resetStats()
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{
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AbstractController::resetStats();
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}
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void
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CHIGenericController::wakeup()
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{
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bool pending = false;
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DPRINTF(RubyCHIGeneric, "wakeup: checking incoming rsp messages\n");
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pending = pending || receiveAllRdyMessages<CHIResponseMsg>(rspIn,
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[this](const CHIResponseMsg* msg){ return recvResponseMsg(msg); });
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DPRINTF(RubyCHIGeneric, "wakeup: checking incoming dat messages\n");
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pending = pending || receiveAllRdyMessages<CHIDataMsg>(datIn,
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[this](const CHIDataMsg* msg){ return recvDataMsg(msg); });
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DPRINTF(RubyCHIGeneric, "wakeup: checking incoming snp messages\n");
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pending = pending || receiveAllRdyMessages<CHIRequestMsg>(snpIn,
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[this](const CHIRequestMsg* msg){ return recvSnoopMsg(msg); });
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DPRINTF(RubyCHIGeneric, "wakeup: checking incoming req messages\n");
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pending = pending || receiveAllRdyMessages<CHIRequestMsg>(reqIn,
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[this](const CHIRequestMsg* msg){ return recvRequestMsg(msg); });
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if (pending) {
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DPRINTF(RubyCHIGeneric, "wakeup: messages pending\n");
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scheduleEvent(Cycles(1));
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}
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}
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void
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CHIGenericController::recordCacheTrace(int cntrl, CacheRecorder* tr)
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{
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panic("CHIGenericController doesn't implement recordCacheTrace");
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}
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AccessPermission
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CHIGenericController::getAccessPermission(const Addr& param_addr)
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{
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return AccessPermission_NotPresent;
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}
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void
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CHIGenericController::functionalRead(
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const Addr& param_addr, Packet* param_pkt, WriteMask& param_mask)
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{
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panic("CHIGenericController doesn't expect functionalRead");
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}
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int
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CHIGenericController::functionalWrite(
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const Addr& param_addr, Packet* param_pkt)
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{
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panic("CHIGenericController doesn't expect functionalRead");
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return 0;
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}
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int
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CHIGenericController::functionalWriteBuffers(PacketPtr& pkt)
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{
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int num_functional_writes = 0;
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num_functional_writes += reqOut->functionalWrite(pkt);
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num_functional_writes += snpOut->functionalWrite(pkt);
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num_functional_writes += rspOut->functionalWrite(pkt);
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num_functional_writes += datOut->functionalWrite(pkt);
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num_functional_writes += reqIn->functionalWrite(pkt);
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num_functional_writes += snpIn->functionalWrite(pkt);
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num_functional_writes += rspIn->functionalWrite(pkt);
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num_functional_writes += datIn->functionalWrite(pkt);
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return num_functional_writes;
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}
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bool
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CHIGenericController::functionalReadBuffers(PacketPtr& pkt)
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{
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if (reqOut->functionalRead(pkt)) return true;
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if (snpOut->functionalRead(pkt)) return true;
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if (rspOut->functionalRead(pkt)) return true;
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if (datOut->functionalRead(pkt)) return true;
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if (reqIn->functionalRead(pkt)) return true;
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if (snpIn->functionalRead(pkt)) return true;
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if (rspIn->functionalRead(pkt)) return true;
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if (datIn->functionalRead(pkt)) return true;
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return false;
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}
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bool
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CHIGenericController::functionalReadBuffers(PacketPtr& pkt, WriteMask &mask)
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{
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bool read = false;
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if (reqOut->functionalRead(pkt, mask)) read = true;
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if (snpOut->functionalRead(pkt, mask)) read = true;
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if (rspOut->functionalRead(pkt, mask)) read = true;
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if (datOut->functionalRead(pkt, mask)) read = true;
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if (reqIn->functionalRead(pkt, mask)) read = true;
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if (snpIn->functionalRead(pkt, mask)) read = true;
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if (rspIn->functionalRead(pkt, mask)) read = true;
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if (datIn->functionalRead(pkt, mask)) read = true;
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return read;
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}
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} // namespace ruby
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} // namespace gem5
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202
src/mem/ruby/protocol/chi/generic/CHIGenericController.hh
Normal file
202
src/mem/ruby/protocol/chi/generic/CHIGenericController.hh
Normal file
@@ -0,0 +1,202 @@
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/*
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* Copyright (c) 2023 ARM Limited
|
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* All rights reserved
|
||||
*
|
||||
* The license below extends only to copyright in the software and shall
|
||||
* not be construed as granting a license to any other intellectual
|
||||
* property including but not limited to intellectual property relating
|
||||
* to a hardware implementation of the functionality of the software
|
||||
* licensed hereunder. You may use the software subject to the license
|
||||
* terms below provided that you ensure that this notice is replicated
|
||||
* unmodified and in its entirety in all distributions of the software,
|
||||
* modified or unmodified, in source code or in binary form.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
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#ifndef __MEM_RUBY_PROTOCOL_CHI_CHIGenericController_HH__
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#define __MEM_RUBY_PROTOCOL_CHI_CHIGenericController_HH__
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#include <iostream>
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#include <sstream>
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#include <string>
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#include "mem/ruby/common/Consumer.hh"
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#include "mem/ruby/network/MessageBuffer.hh"
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#include "mem/ruby/protocol/AccessPermission.hh"
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#include "mem/ruby/slicc_interface/AbstractController.hh"
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#include "mem/ruby/system/CacheRecorder.hh"
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#include "params/CHIGenericController.hh"
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// Generated from SLICC
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#include "mem/ruby/protocol/CHIDataMsg.hh"
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#include "mem/ruby/protocol/CHIRequestMsg.hh"
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#include "mem/ruby/protocol/CHIResponseMsg.hh"
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#include "mem/ruby/protocol/Cache_Controller.hh"
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namespace gem5
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{
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namespace ruby
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{
|
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class CHIGenericController : public AbstractController
|
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{
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public:
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PARAMS(CHIGenericController);
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CHIGenericController(const Params &p);
|
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|
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void init() override;
|
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|
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MessageBuffer *getMandatoryQueue() const override;
|
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MessageBuffer *getMemReqQueue() const override;
|
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MessageBuffer *getMemRespQueue() const override;
|
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void initNetQueues() override;
|
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|
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void print(std::ostream& out) const override;
|
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void wakeup() override;
|
||||
void resetStats() override;
|
||||
void regStats() override;
|
||||
void collateStats() override;
|
||||
|
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void recordCacheTrace(int cntrl, CacheRecorder* tr) override;
|
||||
Sequencer* getCPUSequencer() const override;
|
||||
DMASequencer* getDMASequencer() const override;
|
||||
GPUCoalescer* getGPUCoalescer() const override;
|
||||
|
||||
void addSequencer(RubyPort* seq);
|
||||
|
||||
bool functionalReadBuffers(PacketPtr&) override;
|
||||
bool functionalReadBuffers(PacketPtr&, WriteMask&) override;
|
||||
int functionalWriteBuffers(PacketPtr&) override;
|
||||
|
||||
AccessPermission getAccessPermission(const Addr& param_addr) override;
|
||||
|
||||
void functionalRead(const Addr& param_addr, Packet* param_pkt,
|
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WriteMask& param_mask) override;
|
||||
int functionalWrite(const Addr& param_addr, Packet* param_pkt) override;
|
||||
|
||||
protected:
|
||||
MessageBuffer* const reqOut;
|
||||
MessageBuffer* const snpOut;
|
||||
MessageBuffer* const rspOut;
|
||||
MessageBuffer* const datOut;
|
||||
MessageBuffer* const reqIn;
|
||||
MessageBuffer* const snpIn;
|
||||
MessageBuffer* const rspIn;
|
||||
MessageBuffer* const datIn;
|
||||
|
||||
std::vector<RubyPort*> sequencers;
|
||||
|
||||
public:
|
||||
const int cacheLineSize;
|
||||
const int cacheLineBits;
|
||||
const int dataChannelSize;
|
||||
const int dataMsgsPerLine;
|
||||
|
||||
// interface to generic requesters and responders
|
||||
|
||||
enum CHIChannel
|
||||
{
|
||||
CHI_REQ = 0,
|
||||
CHI_SNP = 1,
|
||||
CHI_RSP = 2,
|
||||
CHI_DAT = 3
|
||||
};
|
||||
|
||||
typedef std::shared_ptr<CHIRequestMsg> CHIRequestMsgPtr;
|
||||
typedef std::shared_ptr<CHIResponseMsg> CHIResponseMsgPtr;
|
||||
typedef std::shared_ptr<CHIDataMsg> CHIDataMsgPtr;
|
||||
|
||||
bool
|
||||
sendRequestMsg(CHIRequestMsgPtr msg)
|
||||
{
|
||||
return sendMessage(msg, reqOut);
|
||||
}
|
||||
|
||||
bool
|
||||
sendSnoopMsg(CHIRequestMsgPtr msg)
|
||||
{
|
||||
return sendMessage(msg, snpOut);
|
||||
}
|
||||
|
||||
bool
|
||||
sendResponseMsg(CHIResponseMsgPtr msg)
|
||||
{
|
||||
return sendMessage(msg, rspOut);
|
||||
}
|
||||
|
||||
bool
|
||||
sendDataMsg(CHIDataMsgPtr msg)
|
||||
{
|
||||
return sendMessage(msg, datOut);
|
||||
}
|
||||
|
||||
protected:
|
||||
virtual bool recvRequestMsg(const CHIRequestMsg *msg) = 0;
|
||||
virtual bool recvSnoopMsg(const CHIRequestMsg *msg) = 0;
|
||||
virtual bool recvResponseMsg(const CHIResponseMsg *msg) = 0;
|
||||
virtual bool recvDataMsg(const CHIDataMsg *msg) = 0;
|
||||
|
||||
private:
|
||||
template<typename MsgType>
|
||||
bool receiveAllRdyMessages(MessageBuffer *buffer,
|
||||
const std::function<bool(const MsgType*)> &callback)
|
||||
{
|
||||
bool pending = false;
|
||||
Tick cur_tick = curTick();
|
||||
while (buffer->isReady(cur_tick)) {
|
||||
const MsgType *msg =
|
||||
dynamic_cast<const MsgType*>(buffer->peek());
|
||||
assert(msg);
|
||||
if (callback(msg))
|
||||
buffer->dequeue(cur_tick);
|
||||
else {
|
||||
pending = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return pending;
|
||||
}
|
||||
|
||||
template<typename MessageType>
|
||||
bool sendMessage(MessageType &msg, MessageBuffer *buffer)
|
||||
{
|
||||
Tick cur_tick = curTick();
|
||||
if (buffer->areNSlotsAvailable(1, cur_tick)) {
|
||||
buffer->enqueue(msg, curTick(), cyclesToTicks(Cycles(1)),
|
||||
m_ruby_system->getRandomization(),
|
||||
m_ruby_system->getWarmupEnabled());
|
||||
return true;
|
||||
} else {
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
} // namespace ruby
|
||||
} // namespace gem5
|
||||
|
||||
#endif // __CHIGenericController_H__
|
||||
49
src/mem/ruby/protocol/chi/generic/SConscript
Normal file
49
src/mem/ruby/protocol/chi/generic/SConscript
Normal file
@@ -0,0 +1,49 @@
|
||||
# -*- mode:python -*-
|
||||
|
||||
# Copyright (c) 2023 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
Import('*')
|
||||
|
||||
if env['CONF']['PROTOCOL'] != 'CHI':
|
||||
Return()
|
||||
|
||||
SimObject('CHIGeneric.py',
|
||||
sim_objects=['CHIGenericController'])
|
||||
|
||||
DebugFlag('RubyCHIGeneric')
|
||||
DebugFlag('RubyCHIGenericVerbose')
|
||||
|
||||
Source('CHIGenericController.cc')
|
||||
Reference in New Issue
Block a user