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dev-arm: Move VGic from Realview.py to Gic.py

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Change-Id: I17f2fb6be2435d4601263e7f68a0582e0cc70838
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15276
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2018-12-20 17:31:42 +00:00
parent b5e0a8f19a
commit 75831ce5b7
2 changed files with 39 additions and 39 deletions
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39
src/dev/arm/Gic.py
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@@ -95,3 +95,42 @@ class Gicv2m(PioDevice):
pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
gic = Param.BaseGic(Parent.any, "Gic on which to trigger interrupts")
frames = VectorParam.Gicv2mFrame([], "Power of two number of frames")
class VGic(PioDevice):
type = 'VGic'
cxx_header = "dev/arm/vgic.hh"
gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
platform = Param.Platform(Parent.any, "Platform this device is part of.")
vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
hv_addr = Param.Addr(0, "Address for hv control")
pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
# The number of list registers is not currently configurable at runtime.
ppint = Param.UInt32("HV maintenance interrupt number")
def generateDeviceTree(self, state):
gic = self.gic.unproxy(self)
node = FdtNode("interrupt-controller")
node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic",
"arm,cortex-a9-gic"])
node.append(FdtPropertyWords("#interrupt-cells", [3]))
node.append(FdtPropertyWords("#address-cells", [0]))
node.append(FdtProperty("interrupt-controller"))
regs = (
state.addrCells(gic.dist_addr) +
state.sizeCells(0x1000) +
state.addrCells(gic.cpu_addr) +
state.sizeCells(0x1000) +
state.addrCells(self.hv_addr) +
state.sizeCells(0x2000) +
state.addrCells(self.vcpu_addr) +
state.sizeCells(0x2000) )
node.append(FdtPropertyWords("reg", regs))
node.append(FdtPropertyWords("interrupts",
[1, int(self.ppint)-16, 0xf04]))
node.appendPhandle(gic)
yield node

39
src/dev/arm/RealView.py
View File

@@ -324,45 +324,6 @@ ARM DUI 0604E for details.
yield node
class VGic(PioDevice):
type = 'VGic'
cxx_header = "dev/arm/vgic.hh"
gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
platform = Param.Platform(Parent.any, "Platform this device is part of.")
vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
hv_addr = Param.Addr(0, "Address for hv control")
pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
# The number of list registers is not currently configurable at runtime.
ppint = Param.UInt32("HV maintenance interrupt number")
def generateDeviceTree(self, state):
gic = self.gic.unproxy(self)
node = FdtNode("interrupt-controller")
node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic",
"arm,cortex-a9-gic"])
node.append(FdtPropertyWords("#interrupt-cells", [3]))
node.append(FdtPropertyWords("#address-cells", [0]))
node.append(FdtProperty("interrupt-controller"))
regs = (
state.addrCells(gic.dist_addr) +
state.sizeCells(0x1000) +
state.addrCells(gic.cpu_addr) +
state.sizeCells(0x1000) +
state.addrCells(self.hv_addr) +
state.sizeCells(0x2000) +
state.addrCells(self.vcpu_addr) +
state.sizeCells(0x2000) )
node.append(FdtPropertyWords("reg", regs))
node.append(FdtPropertyWords("interrupts",
[1, int(self.ppint)-16, 0xf04]))
node.appendPhandle(gic)
yield node
class AmbaFake(AmbaPioDevice):
type = 'AmbaFake'
cxx_header = "dev/arm/amba_fake.hh"