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arch-vega: Update Vega instruction flags

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The instructions file seems to be assuming a newer pipeline which is not
released. The flags are therefore not set in Vega as the newer pipeline
infers them. This adds back flags for MemoryRef instructions, fixes
waitcnt and removes CondBranch which was not checked and changed to
Branch.

This also removeds unused Cac flags and fixes the casing for ReadsEXEC
and WritesEXEC. The remaining flags are not used at all by the pipeline
and are removed to avoid confusion as to whether these are needed for
GCN3 or not.

Change-Id: I976cbd407a466e8ad77c84dbdc29082f49e28f3b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47102
Reviewed-by: Kyle Roarty <kyleroarty1716@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Matthew Poremba
2021-06-22 18:35:22 -05:00
parent 26caffd0d4
commit 753a2c8aac
2 changed files with 603 additions and 369 deletions
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955
src/arch/amdgpu/vega/insts/instructions.cc
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File diff suppressed because it is too large Load Diff

17
src/arch/amdgpu/vega/insts/op_encodings.cc
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@@ -482,7 +482,7 @@ namespace VegaISA
: VEGAGPUStaticInst(opcode)
{
setFlag(Scalar);
setFlag(SMEM);
setFlag(GlobalSegment);
// copy first instruction DWORD
instData = iFmt[0];
@@ -491,7 +491,7 @@ namespace VegaISA
_srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
if (instData.GLC)
setFlag(GroupCoherent);
setFlag(GloballyCoherent);
} // Inst_SMEM
Inst_SMEM::~Inst_SMEM()
@@ -1152,7 +1152,7 @@ namespace VegaISA
Inst_DS::Inst_DS(InFmt_DS *iFmt, const std::string &opcode)
: VEGAGPUStaticInst(opcode)
{
setFlag(LDS);
setFlag(GroupSegment);
// copy first instruction DWORD
instData = iFmt[0];
@@ -1237,10 +1237,9 @@ namespace VegaISA
// copy second instruction DWORD
extData = ((InFmt_MUBUF_1 *)iFmt)[1];
_srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
setFlag(TextureMem);
if (instData.GLC)
setFlag(GroupCoherent);
setFlag(GloballyCoherent);
if (instData.SLC)
setFlag(SystemCoherent);
@@ -1331,10 +1330,9 @@ namespace VegaISA
// copy second instruction DWORD
extData = ((InFmt_MTBUF_1 *)iFmt)[1];
_srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
setFlag(TextureMem);
if (instData.GLC)
setFlag(GroupCoherent);
setFlag(GloballyCoherent);
if (extData.SLC)
setFlag(SystemCoherent);
@@ -1404,10 +1402,9 @@ namespace VegaISA
// copy second instruction DWORD
extData = ((InFmt_MIMG_1 *)iFmt)[1];
_srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
setFlag(TextureMem);
if (instData.GLC)
setFlag(GroupCoherent);
setFlag(GloballyCoherent);
if (instData.SLC)
setFlag(SystemCoherent);
@@ -1523,7 +1520,7 @@ namespace VegaISA
_srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
if (instData.GLC)
setFlag(GroupCoherent);
setFlag(GloballyCoherent);
if (instData.SLC)
setFlag(SystemCoherent);