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mem: Add a DDR5 memory interface

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This change adds a single DDR5 memory inteface.
A DDR5 DIMM contains two physical channels. Therefore,
two instances of this interface should be used to model
a DDR5 DIMM. The configuration includes 3 different speed
bins models. The configuration is tested with different
types of memory traffic using the traffic generator and shows
performance similar to what is observed in existing
literature [1]. One of the key features of DDR5
"same bank refresh" is yet not supported in gem5, but is
expected to improve the performance of the DDR5 model.

[1] Exploration of DDR5 with the Open-Source Simulator DRAMSys.

Change-Id: I5856a10c8dcd92dbecc7fd4dcea0f674b2412dd7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68257
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Ayaz Akram
2023-02-21 15:16:38 -08:00
parent e0a28b1a27
commit 741af7ddae
5 changed files with 588 additions and 7 deletions
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src/python/SConscript
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@@ -185,6 +185,8 @@ PySource('gem5.components.memory.dram_interfaces',
'gem5/components/memory/dram_interfaces/ddr3.py')
PySource('gem5.components.memory.dram_interfaces',
'gem5/components/memory/dram_interfaces/ddr4.py')
PySource('gem5.components.memory.dram_interfaces',
'gem5/components/memory/dram_interfaces/ddr5.py')
PySource('gem5.components.memory.dram_interfaces',
'gem5/components/memory/dram_interfaces/gddr.py')
PySource('gem5.components.memory.dram_interfaces',