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inorder: DynInst handling of stores for big-endian ISAs

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The DynInst was not performing the host-to-guest translation
which ended up breaking stores for SPARC
This commit is contained in:
Korey Sewell
2011-06-19 21:43:35 -04:00
parent 4f34bc8b7b
commit 73cfab8b23
2 changed files with 14 additions and 5 deletions
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13
src/cpu/inorder/inorder_dyn_inst.cc
View File

@@ -527,7 +527,10 @@ InOrderDynInst::read(Addr addr, T &data, unsigned flags)
traceData->setData(data);
}
Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
DPRINTF(InOrderDynInst, "[sn:%i] (1) Received Bytes %x\n", seqNum, data);
data = TheISA::gtoh(data);
DPRINTF(InOrderDynInst, "[sn%:i] (2) Received Bytes %x\n", seqNum, data);
if (traceData)
traceData->setData(data);
return fault;
@@ -588,6 +591,8 @@ InOrderDynInst::writeBytes(uint8_t *data, unsigned size,
{
assert(sizeof(storeData) >= size);
memcpy(&storeData, data, size);
DPRINTF(InOrderDynInst, "(2) [tid:%i]: [sn:%i] Setting store data to %#x.\n",
threadNumber, seqNum, storeData);
return cpu->write(this, (uint8_t *)&storeData, size, addr, flags, res);
}
@@ -595,15 +600,13 @@ template<class T>
inline Fault
InOrderDynInst::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
storeData = data;
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting store data to %#x.\n",
threadNumber, seqNum, storeData);
if (traceData) {
traceData->setAddr(addr);
traceData->setData(data);
}
storeData = TheISA::htog(data);
data = TheISA::htog(data);
DPRINTF(InOrderDynInst, "(1) [tid:%i]: [sn:%i] Setting store data to %#x.\n",
threadNumber, seqNum, data);
return writeBytes((uint8_t*)&data, sizeof(T), addr, flags, res);
}

6
src/cpu/inorder/resources/cache_unit.cc
View File

@@ -840,6 +840,12 @@ CacheUnit::doCacheAccess(DynInstPtr inst, uint64_t *write_res,
} else {
cache_req->dataPkt->dataStatic(&cache_req->inst->storeData);
}
DPRINTF(InOrderCachePort,
"[tid:%u]: [sn:%i]: Storing data: %s\n",
tid, inst->seqNum,
printMemData(cache_req->dataPkt->getPtr<uint8_t>(),
cache_req->dataPkt->getSize()));
if (cache_req->memReq->isCondSwap()) {
assert(write_res);