Ruby: Remove files and includes not in use

This commit is contained in:
Nilay Vaish
2011-08-03 18:25:30 -05:00
parent 6230668f5e
commit 720c0be620
19 changed files with 0 additions and 98 deletions

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@@ -130,7 +130,6 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
MessageBuffer mandatoryQueue, ordered="false";
int cache_state_to_int(State state);
int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
void set_cache_entry(AbstractCacheEntry a);

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@@ -34,7 +34,6 @@
#include "base/hashmap.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/system/MachineID.hh"
#include "mem/ruby/system/NodeID.hh"
const int ADDRESS_WIDTH = 64; // address width in bytes

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@@ -26,7 +26,6 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/protocol/Protocol.hh"
#include "mem/ruby/common/NetDest.hh"
NetDest::NetDest()

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@@ -30,7 +30,6 @@
#include "debug/RubyNetwork.hh"
#include "mem/protocol/MachineType.hh"
#include "mem/protocol/Protocol.hh"
#include "mem/protocol/TopologyType.hh"
#include "mem/ruby/common/NetDest.hh"
#include "mem/ruby/network/BasicLink.hh"

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@@ -29,7 +29,6 @@
#include <algorithm>
#include "debug/RubyNetwork.hh"
#include "mem/protocol/Protocol.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/network/simple/PerfectSwitch.hh"
#include "mem/ruby/network/simple/SimpleNetwork.hh"

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@@ -31,7 +31,6 @@
#include "base/stl_helpers.hh"
#include "mem/protocol/MachineType.hh"
#include "mem/protocol/Protocol.hh"
#include "mem/protocol/TopologyType.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/common/NetDest.hh"

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@@ -30,7 +30,6 @@
#include "base/stl_helpers.hh"
#include "mem/protocol/MessageSizeType.hh"
#include "mem/protocol/Protocol.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/network/simple/PerfectSwitch.hh"
#include "mem/ruby/network/simple/SimpleNetwork.hh"

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@@ -30,7 +30,6 @@
#include "base/cprintf.hh"
#include "debug/RubyNetwork.hh"
#include "mem/protocol/Protocol.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/network/simple/Throttle.hh"
#include "mem/ruby/network/Network.hh"

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@@ -52,7 +52,6 @@
#include "base/stl_helpers.hh"
#include "base/str.hh"
#include "mem/protocol/MachineType.hh"
#include "mem/protocol/Protocol.hh"
#include "mem/protocol/RubyRequest.hh"
#include "mem/ruby/network/Network.hh"
#include "mem/ruby/profiler/AddressProfiler.hh"

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@@ -66,4 +66,3 @@ operator<<(std::ostream& out, const AbstractEntry& obj)
}
#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTENTRY_HH__

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@@ -1,30 +0,0 @@
/*
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
#include "mem/ruby/system/CacheMemory.hh"

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@@ -34,7 +34,6 @@
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/common/NetDest.hh"
#include "mem/ruby/common/Set.hh"
#include "mem/ruby/system/DirectoryMemory.hh"
#include "mem/ruby/system/MachineID.hh"
#include "mem/ruby/system/NodeID.hh"

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@@ -26,7 +26,6 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/protocol/Protocol.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/profiler/AddressProfiler.hh"
#include "mem/ruby/profiler/Profiler.hh"
@@ -36,17 +35,6 @@
using namespace std;
void
profile_request(int cache_state, Directory_State directory_state,
GenericRequestType request_type)
{
string requestStr = L1Cache_State_to_string(L1Cache_State(cache_state))+
":" +
Directory_State_to_string(directory_state) + ":" +
GenericRequestType_to_string(request_type);
g_system_ptr->getProfiler()->profileRequest(requestStr);
}
void
profile_request(const string& L1CacheState, const string& L2CacheState,
const string& directoryState, const string& requestType)

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@@ -36,9 +36,6 @@
#include <string>
#include "mem/protocol/AccessType.hh"
#include "mem/protocol/Directory_State.hh"
#include "mem/protocol/GenericRequestType.hh"
#include "mem/protocol/L1Cache_State.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/profiler/Profiler.hh"
@@ -46,8 +43,6 @@
class Set;
void profile_request(int cache_state, Directory_State directory_state,
GenericRequestType request_type);
void profile_outstanding_persistent_request(int outstanding);
void profile_outstanding_request(int outstanding);
void profile_sharing(const Address& addr, AccessType type, NodeID requestor,

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@@ -36,9 +36,7 @@
#include <cassert>
#include "mem/protocol/AccessType.hh"
#include "mem/protocol/Directory_State.hh"
#include "mem/protocol/GenericRequestType.hh"
#include "mem/protocol/L1Cache_State.hh"
#include "mem/protocol/MachineType.hh"
#include "mem/protocol/MessageSizeType.hh"
#include "mem/protocol/PrefetchBit.hh"
@@ -69,12 +67,6 @@ multicast_retry()
}
}
inline int
cache_state_to_int(L1Cache_State state)
{
return state;
}
inline Time
get_time()
{

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@@ -40,4 +40,3 @@ Source('AbstractEntry.cc')
Source('AbstractCacheEntry.cc')
Source('RubyRequest.cc')
Source('RubySlicc_Profiler_interface.cc')
Source('RubySlicc_ComponentMapping.cc')

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@@ -184,34 +184,6 @@ DirectoryMemory::lookup(PhysAddress address)
return *entry;
}
#if 0
Directory_Entry&
DirectoryMemory::lookup(PhysAddress address)
{
assert(isPresent(address));
Index index = address.memoryModuleIndex();
if (index < 0 || index > m_size) {
WARN_EXPR(address.getAddress());
WARN_EXPR(index);
WARN_EXPR(m_size);
ERROR_MSG("Directory Memory Assertion: accessing memory out of range");
}
Directory_Entry* entry = m_entries[index];
// allocate the directory entry on demand.
if (entry == NULL) {
entry = new Directory_Entry;
entry->getDataBlk().assign(m_ram->getBlockPtr(address));
// store entry to the table
m_entries[index] = entry;
}
return *entry;
}
#endif
void
DirectoryMemory::invalidateBlock(PhysAddress address)
{

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@@ -31,7 +31,6 @@
#include "cpu/testers/rubytest/RubyTester.hh"
#include "debug/MemoryAccess.hh"
#include "debug/ProtocolTrace.hh"
#include "mem/protocol/Protocol.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/common/SubBlock.hh"

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@@ -44,7 +44,6 @@
#include "sim/sim_object.hh"
class AbstractController;
class AbstractMemory;
class CacheRecorder;
class MemoryVector;
class Network;
@@ -134,7 +133,6 @@ class RubySystem : public SimObject
void registerNetwork(Network*);
void registerProfiler(Profiler*);
void registerTracer(Tracer*);
void registerAbstractMemory(AbstractMemory*);
void registerAbstractController(AbstractController*);
private: