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arch-arm: implement the aarch64 ID_ISAR6_EL1 miscregister

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This register is used since the Linux kernel 5.6 aarch64 boot.

This register indicates CPU capabilities in aarch32 mode, and it has the
same value as the aarch32 ID_ISAR6 miscregister, which is also added.

The capability values of those registers are analogous to those present in
aarch64 accessible ID_AA64ISAR0_EL1 and ID_AA64ISAR1_EL1, which refer to
aarch64 capabilities however, and were already implemented before this
commit.

The arm architecture document clarifies that reads to this system register
location before it had been defined should return 0, but we were faulting
instead:

> Prior to the introduction of the features described by this register,
this register was unnamed and reserved, RES0 from EL1, EL2, and EL3.

Change-Id: I70e99536dc98925e88233fd4c6887bbcdd5d87dc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30935
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Ciro Santilli
2020-06-05 11:02:46 +01:00
parent 0ff49d741c
commit 7209a44e0a
9 changed files with 27 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/arch/arm/ArmISA.py
View File

@@ -81,6 +81,8 @@ class ArmISA(BaseISA):
id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3")
id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4")
id_isar5 = Param.UInt32(0x11000000, "Instruction Set Attribute Register 5")
# !I8MM | !BF16 | SPECRES = 0 | !SB | !FHM | DP | JSCVT
id_isar6 = Param.UInt32(0x00000001, "Instruction Set Attribute Register 6")
fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register")
@@ -98,10 +100,11 @@ class ArmISA(BaseISA):
id_aa64dfr1_el1 = Param.UInt64(0x0000000000000000,
"AArch64 Debug Feature Register 1")
# !TME | !Atomic | !CRC32 | !SHA2 | RDM | !SHA1 | !AES
# !FHM | !TME | !Atomic | !CRC32 | !SHA2 | RDM | !SHA1 | !AES
id_aa64isar0_el1 = Param.UInt64(0x0000000010000000,
"AArch64 Instruction Set Attribute Register 0")
# !I8MM | !BF16 | SPECRES = 0 | !SB |
# GPI = 0x0 | GPA = 0x1 | API=0x0 | FCMA | JSCVT | APA=0x1
id_aa64isar1_el1 = Param.UInt64(0x0000000001011010,
"AArch64 Instruction Set Attribute Register 1")

2
src/arch/arm/fastmodel/CortexA76/thread_context.cc
View File

@@ -306,6 +306,7 @@ Iris::ThreadContext::IdxNameMap CortexA76TC::miscRegIdxNameMap({
{ ArmISA::MISCREG_ID_ISAR3, "ID_ISAR3" },
{ ArmISA::MISCREG_ID_ISAR4, "ID_ISAR4" },
{ ArmISA::MISCREG_ID_ISAR5, "ID_ISAR5" },
{ ArmISA::MISCREG_ID_ISAR6, "ID_ISAR6" },
{ ArmISA::MISCREG_CCSIDR, "CCSIDR" },
{ ArmISA::MISCREG_CLIDR, "CLIDR" },
{ ArmISA::MISCREG_AIDR, "AIDR" },
@@ -587,6 +588,7 @@ Iris::ThreadContext::IdxNameMap CortexA76TC::miscRegIdxNameMap({
{ ArmISA::MISCREG_ID_ISAR3_EL1, "ID_ISAR3_EL1" },
{ ArmISA::MISCREG_ID_ISAR4_EL1, "ID_ISAR4_EL1" },
{ ArmISA::MISCREG_ID_ISAR5_EL1, "ID_ISAR5_EL1" },
{ ArmISA::MISCREG_ID_ISAR6_EL1, "ID_ISAR6_EL1" },
{ ArmISA::MISCREG_MVFR0_EL1, "MVFR0_EL1" },
{ ArmISA::MISCREG_MVFR1_EL1, "MVFR1_EL1" },
{ ArmISA::MISCREG_MVFR2_EL1, "MVFR2_EL1" },

1
src/arch/arm/insts/misc64.cc
View File

@@ -372,6 +372,7 @@ MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
case MISCREG_ID_ISAR3_EL1:
case MISCREG_ID_ISAR4_EL1:
case MISCREG_ID_ISAR5_EL1:
case MISCREG_ID_ISAR6_EL1:
case MISCREG_MVFR0_EL1:
case MISCREG_MVFR1_EL1:
case MISCREG_MVFR2_EL1:

1
src/arch/arm/isa.cc
View File

@@ -344,6 +344,7 @@ ISA::initID32(const ArmISAParams &p)
miscRegs[MISCREG_ID_ISAR3] = p.id_isar3;
miscRegs[MISCREG_ID_ISAR4] = p.id_isar4;
miscRegs[MISCREG_ID_ISAR5] = p.id_isar5;
miscRegs[MISCREG_ID_ISAR6] = p.id_isar6;
miscRegs[MISCREG_ID_MMFR0] = p.id_mmfr0;
miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1;

3
src/arch/arm/kvm/arm_cpu.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012 ARM Limited
* Copyright (c) 2012, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -157,6 +157,7 @@ static uint64_t invariant_reg_vector[] = {
REG_CP32(15, 0, 0, 2, 3), // ID_ISAR3
REG_CP32(15, 0, 0, 2, 4), // ID_ISAR4
REG_CP32(15, 0, 0, 2, 5), // ID_ISAR5
REG_CP32(15, 0, 0, 2, 7), // ID_ISAR6
REG_CP32(15, 0, 1, 0, 0), // CSSIDR
REG_CP32(15, 0, 1, 0, 1), // CLIDR

10
src/arch/arm/miscregs.cc
View File

@@ -394,8 +394,9 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
case 5:
return MISCREG_ID_ISAR5;
case 6:
case 7:
return MISCREG_RAZ; // read as zero
case 7:
return MISCREG_ID_ISAR6;
}
break;
default:
@@ -2059,6 +2060,8 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
return MISCREG_ID_ISAR4_EL1;
case 5:
return MISCREG_ID_ISAR5_EL1;
case 7:
return MISCREG_ID_ISAR6_EL1;
}
break;
case 3:
@@ -3779,6 +3782,8 @@ ISA::initializeMiscRegMetadata()
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_ISAR5)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_ISAR6)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_CCSIDR)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_CLIDR)
@@ -4708,6 +4713,9 @@ ISA::initializeMiscRegMetadata()
InitReg(MISCREG_ID_ISAR5_EL1)
.allPrivileges().exceptUserMode().writes(0)
.mapsTo(MISCREG_ID_ISAR5);
InitReg(MISCREG_ID_ISAR6_EL1)
.allPrivileges().exceptUserMode().writes(0)
.mapsTo(MISCREG_ID_ISAR6);
InitReg(MISCREG_MVFR0_EL1)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_MVFR1_EL1)

4
src/arch/arm/miscregs.hh
View File

@@ -218,6 +218,7 @@ namespace ArmISA
MISCREG_ID_ISAR3,
MISCREG_ID_ISAR4,
MISCREG_ID_ISAR5,
MISCREG_ID_ISAR6,
MISCREG_CCSIDR,
MISCREG_CLIDR,
MISCREG_AIDR,
@@ -547,6 +548,7 @@ namespace ArmISA
MISCREG_ID_ISAR3_EL1,
MISCREG_ID_ISAR4_EL1,
MISCREG_ID_ISAR5_EL1,
MISCREG_ID_ISAR6_EL1,
MISCREG_MVFR0_EL1,
MISCREG_MVFR1_EL1,
MISCREG_MVFR2_EL1,
@@ -1321,6 +1323,7 @@ namespace ArmISA
"id_isar3",
"id_isar4",
"id_isar5",
"id_isar6",
"ccsidr",
"clidr",
"aidr",
@@ -1648,6 +1651,7 @@ namespace ArmISA
"id_isar3_el1",
"id_isar4_el1",
"id_isar5_el1",
"id_isar6_el1",
"mvfr0_el1",
"mvfr1_el1",
"mvfr2_el1",

4
src/arch/arm/tracers/tarmac_parser.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2011,2017-2019 ARM Limited
* Copyright (c) 2011,2017-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -206,6 +206,7 @@ TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = {
{ "id_isar3", MISCREG_ID_ISAR3 },
{ "id_isar4", MISCREG_ID_ISAR4 },
{ "id_isar5", MISCREG_ID_ISAR5 },
{ "id_isar6", MISCREG_ID_ISAR6 },
{ "ccsidr", MISCREG_CCSIDR },
{ "clidr", MISCREG_CLIDR },
{ "aidr", MISCREG_AIDR },
@@ -504,6 +505,7 @@ TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = {
{ "id_isar3_el1", MISCREG_ID_ISAR3_EL1 },
{ "id_isar4_el1", MISCREG_ID_ISAR4_EL1 },
{ "id_isar5_el1", MISCREG_ID_ISAR5_EL1 },
{ "id_isar6_el1", MISCREG_ID_ISAR6_EL1 },
{ "mvfr0_el1", MISCREG_MVFR0_EL1 },
{ "mvfr1_el1", MISCREG_MVFR1_EL1 },
{ "mvfr2_el1", MISCREG_MVFR2_EL1 },

1
src/arch/arm/utility.cc
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@@ -665,6 +665,7 @@ mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss,
case MISCREG_ID_ISAR3:
case MISCREG_ID_ISAR4:
case MISCREG_ID_ISAR5:
case MISCREG_ID_ISAR6:
trapToHype = hcr.tid3;
break;
case MISCREG_DCISW: