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stdlib: Clarify power of 2 vs power of 10

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This commit changes files in src/python/gem5 so that memory and
cache sizes use "KiB", "MiB", and "GiB" instead of "KB", etc. This
makes the codebase more consistent, as gem5 will automatically
convert memory and cache sizes that are in metric units (KB) to
binary units (KiB).

Change-Id: If5b1e908ddcff7182b71e789229a3ba1fa6ad1f1
This commit is contained in:
Erin Le
2024-08-19 17:46:19 +00:00
committed by Erin (Jianghua) Le
parent fec28e466e
commit 70c8081107
18 changed files with 60 additions and 60 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/python/gem5/components/boards/x86_board.py
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@@ -67,7 +67,7 @@ class X86Board(AbstractSystemBoard, KernelDiskWorkload):
A board capable of full system simulation for X86.
**Limitations**
* Currently, this board's memory is hardcoded to 3GB.
* Currently, this board's memory is hardcoded to 3GiB.
* Much of the I/O subsystem is hard coded.
"""
@@ -238,8 +238,8 @@ class X86Board(AbstractSystemBoard, KernelDiskWorkload):
entries = [
# Mark the first megabyte of memory as reserved
X86E820Entry(addr=0, size="639kB", range_type=1),
X86E820Entry(addr=0x9FC00, size="385kB", range_type=2),
X86E820Entry(addr=0, size="639KiB", range_type=1),
X86E820Entry(addr=0x9FC00, size="385KiB", range_type=2),
# Mark the rest of physical memory as available
X86E820Entry(
addr=0x100000,
@@ -248,9 +248,9 @@ class X86Board(AbstractSystemBoard, KernelDiskWorkload):
),
]
# Reserve the last 16kB of the 32-bit address space for m5ops
# Reserve the last 16KiB of the 32-bit address space for m5ops
entries.append(
X86E820Entry(addr=0xFFFF0000, size="64kB", range_type=2)
X86E820Entry(addr=0xFFFF0000, size="64KiB", range_type=2)
)
self.workload.e820_table.entries = entries
@@ -283,10 +283,10 @@ class X86Board(AbstractSystemBoard, KernelDiskWorkload):
def _setup_memory_ranges(self):
memory = self.get_memory()
if memory.get_size() > toMemorySize("3GB"):
if memory.get_size() > toMemorySize("3GiB"):
raise Exception(
"X86Board currently only supports memory sizes up "
"to 3GB because of the I/O hole."
"to 3GiB because of the I/O hole."
)
data_range = AddrRange(memory.get_size())
memory.set_memory_range([data_range])

6
src/python/gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py
View File

@@ -41,15 +41,15 @@ class AbstractTwoLevelCacheHierarchy:
l2_assoc: int,
):
"""
:param l1i_size: The size of the L1 Instruction cache (e.g. "32kB").
:param l1i_size: The size of the L1 Instruction cache (e.g. "32KiB").
:param l1i_assoc:
:param l1d_size: The size of the L1 Data cache (e.g. "32kB").
:param l1d_size: The size of the L1 Data cache (e.g. "32KiB").
:param l1d_assoc:
:param l2_size: The size of the L2 cache (e.g., "256kB").
:param l2_size: The size of the L2 cache (e.g., "256KiB").
:param l2_assoc:
"""

6
src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
View File

@@ -69,9 +69,9 @@ class PrivateL1CacheHierarchy(AbstractClassicCacheHierarchy):
membus: Optional[BaseXBar] = None,
) -> None:
"""
:param l1d_size: The size of the L1 Data Cache (e.g., "32kB").
:param l1d_size: The size of the L1 Data Cache (e.g., "32KiB").
:param l1i_size: The size of the L1 Instruction Cache (e.g., "32kB").
:param l1i_size: The size of the L1 Instruction Cache (e.g., "32KiB").
:param membus: The memory bus. This parameter is optional parameter and
will default to a 64 bit width SystemXBar is not
@@ -151,7 +151,7 @@ class PrivateL1CacheHierarchy(AbstractClassicCacheHierarchy):
data_latency=50,
response_latency=50,
mshrs=20,
size="1kB",
size="1KiB",
tgts_per_mshr=12,
addr_ranges=board.mem_ranges,
)

8
src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
View File

@@ -89,11 +89,11 @@ class PrivateL1PrivateL2CacheHierarchy(
membus: Optional[BaseXBar] = None,
) -> None:
"""
:param l1d_size: The size of the L1 Data Cache (e.g., "32kB").
:param l1d_size: The size of the L1 Data Cache (e.g., "32KiB").
:param l1i_size: The size of the L1 Instruction Cache (e.g., "32kB").
:param l1i_size: The size of the L1 Instruction Cache (e.g., "32KiB").
:param l2_size: The size of the L2 Cache (e.g., "256kB").
:param l2_size: The size of the L2 Cache (e.g., "256KiB").
:param membus: The memory bus. This parameter is optional parameter and
will default to a 64 bit width SystemXBar is not
@@ -178,7 +178,7 @@ class PrivateL1PrivateL2CacheHierarchy(
data_latency=50,
response_latency=50,
mshrs=20,
size="1kB",
size="1KiB",
tgts_per_mshr=12,
addr_ranges=board.mem_ranges,
)

8
src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py
View File

@@ -82,9 +82,9 @@ class PrivateL1SharedL2CacheHierarchy(
membus: Optional[BaseXBar] = None,
) -> None:
"""
:param l1d_size: The size of the L1 Data Cache (e.g., "32kB").
:param l1i_size: The size of the L1 Instruction Cache (e.g., "32kB").
:param l2_size: The size of the L2 Cache (e.g., "256kB").
:param l1d_size: The size of the L1 Data Cache (e.g., "32KiB").
:param l1i_size: The size of the L1 Instruction Cache (e.g., "32KiB").
:param l2_size: The size of the L2 Cache (e.g., "256KiB").
:param l1d_assoc: The associativity of the L1 Data Cache.
:param l1i_assoc: The associativity of the L1 Instruction Cache.
:param l2_assoc: The associativity of the L2 Cache.
@@ -181,7 +181,7 @@ class PrivateL1SharedL2CacheHierarchy(
data_latency=50,
response_latency=50,
mshrs=20,
size="1kB",
size="1KiB",
tgts_per_mshr=12,
addr_ranges=board.mem_ranges,
)

2
src/python/gem5/components/memory/dram_interfaces/ddr3.py
View File

@@ -67,7 +67,7 @@ class DDR3_1600_8x8(DRAMInterface):
# DDR3 is a BL8 device
burst_length = 8
# Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
# Each device has a page (row buffer) size of 1 Kibibyte (1Ki columns x8)
device_rowbuffer_size = "1KiB"
# 8x8 configuration, so 8 devices

4
src/python/gem5/components/memory/dram_interfaces/ddr4.py
View File

@@ -181,7 +181,7 @@ class DDR4_2400_8x8(DDR4_2400_16x4):
# 8x8 configuration, 8 devices each with an 8-bit interface
device_bus_width = 8
# Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
# Each device has a page (row buffer) size of 1 Kibibyte (1K columns x8)
device_rowbuffer_size = "1KiB"
# 8x8 configuration, so 8 devices
@@ -214,7 +214,7 @@ class DDR4_2400_4x16(DDR4_2400_16x4):
# 4x16 configuration, 4 devices each with an 16-bit interface
device_bus_width = 16
# Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
# Each device has a page (row buffer) size of 2 Kibibyte (1K columns x16)
device_rowbuffer_size = "2KiB"
# 4x16 configuration, so 4 devices

2
src/python/gem5/components/memory/dram_interfaces/ddr5.py
View File

@@ -50,7 +50,7 @@ class DDR5_4400_4x8(DRAMInterface):
burst_length = 16
# Each device has a page (row buffer) size of 256B
# Four devices lead to a page size of 1KB
# Four devices lead to a page size of 1KiB
device_rowbuffer_size = "256B"
# 4Gbx8 configuration

2
src/python/gem5/components/memory/dram_interfaces/gddr.py
View File

@@ -65,7 +65,7 @@ class GDDR5_4000_2x32(DRAMInterface):
# GDDR5 is a BL8 device
burst_length = 8
# Each device has a page (row buffer) size of 2Kbits (256Bytes)
# Each device has a page (row buffer) size of 2Kibibits (256Bytes)
device_rowbuffer_size = "256B"
# 2x32 configuration, so 2 devices

2
src/python/gem5/components/memory/dram_interfaces/hmc.py
View File

@@ -60,7 +60,7 @@ class HMC_2500_1x32(DDR3_1600_8x8):
[2] High performance AXI-4.0 based interconnect for extensible smart memory
cubes (E. Azarkhish et. al).
Assumed for the HMC model is a 30 nm technology node.
The modelled HMC consists of 4 Gbit layers which sum up to 2GiB of memory
The modelled HMC consists of 4 Gibibit layers which sum up to 2GiB of memory
(4 layers).
Each layer has 16 vaults and each vault consists of 2 banks per layer.
In order to be able to use the same controller used for 2D DRAM generations

2
src/python/gem5/components/memory/dram_interfaces/lpddr2.py
View File

@@ -69,7 +69,7 @@ class LPDDR2_S4_1066_1x32(DRAMInterface):
# LPDDR2_S4 is a BL4 and BL8 device
burst_length = 8
# Each device has a page (row buffer) size of 1KB
# Each device has a page (row buffer) size of 1KiB
# (this depends on the memory density)
device_rowbuffer_size = "1KiB"

2
src/python/gem5/components/memory/dram_interfaces/lpddr3.py
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@@ -69,7 +69,7 @@ class LPDDR3_1600_1x32(DRAMInterface):
# LPDDR3 is a BL8 device
burst_length = 8
# Each device has a page (row buffer) size of 4KB
# Each device has a page (row buffer) size of 4KiB
device_rowbuffer_size = "4KiB"
# 1x32 configuration, so 1 device

2
src/python/gem5/components/memory/dram_interfaces/wideio.py
View File

@@ -68,7 +68,7 @@ class WideIO_200_1x128(DRAMInterface):
# This is a BL4 device
burst_length = 4
# Each device has a page (row buffer) size of 4KB
# Each device has a page (row buffer) size of 4KiB
# (this depends on the memory density)
device_rowbuffer_size = "4KiB"

16
src/python/gem5/components/memory/dramsim_3.py
View File

@@ -140,38 +140,38 @@ class SingleChannel(AbstractMemorySystem):
def SingleChannelDDR3_1600(
size: Optional[str] = "2048MB",
size: Optional[str] = "2048MiB",
) -> SingleChannel:
"""
A single channel DDR3_1600.
:param size: The size of the memory system. Default value of 2048MB.
:param size: The size of the memory system. Default value of 2048MiB.
"""
return SingleChannel("DDR3_8Gb_x8_1600", size)
def SingleChannelDDR4_2400(size: Optional[str] = "1024MB") -> SingleChannel:
def SingleChannelDDR4_2400(size: Optional[str] = "1024MiB") -> SingleChannel:
"""
A single channel DDR3_2400.
:param size: The size of the memory system. Default value of 1024MB.
:param size: The size of the memory system. Default value of 1024MiB.
"""
return SingleChannel("DDR4_4Gb_x8_2400", size)
def SingleChannelLPDDR3_1600(size: Optional[str] = "256MB") -> SingleChannel:
def SingleChannelLPDDR3_1600(size: Optional[str] = "256MiB") -> SingleChannel:
"""
A single channel LPDDR3_1600.
:param size: The size of the memory system. Default value of 256MB.
:param size: The size of the memory system. Default value of 256MiB.
"""
return SingleChannel("LPDDR3_8Gb_x32_1600", size)
def SingleChannelHBM(size: Optional[str] = "64MB") -> SingleChannel:
def SingleChannelHBM(size: Optional[str] = "64MiB") -> SingleChannel:
"""
A single channel HBM.
:param size: The size of the memory system. Default value of 64MB.
:param size: The size of the memory system. Default value of 64MiB.
"""
return SingleChannel("HBM1_4Gb_x128", size)

8
src/python/gem5/components/memory/dramsys.py
View File

@@ -133,7 +133,7 @@ class DRAMSysDDR4_1866(DRAMSysMem):
configuration=(
DEFAULT_DRAMSYS_DIRECTORY / "configs/ddr4-example.json"
).as_posix(),
size="4GB",
size="4GiB",
recordable=recordable,
)
@@ -151,7 +151,7 @@ class DRAMSysDDR3_1600(DRAMSysMem):
configuration=(
DEFAULT_DRAMSYS_DIRECTORY / "configs/ddr3-gem5-se.json"
).as_posix(),
size="1GB",
size="1GiB",
recordable=recordable,
)
@@ -169,7 +169,7 @@ class DRAMSysLPDDR4_3200(DRAMSysMem):
configuration=(
DEFAULT_DRAMSYS_DIRECTORY / "configs/lpddr4-example.json"
).as_posix(),
size="1GB",
size="1GiB",
recordable=recordable,
)
@@ -187,6 +187,6 @@ class DRAMSysHBM2(DRAMSysMem):
configuration=(
DEFAULT_DRAMSYS_DIRECTORY / "configs/hbm2-example.json"
).as_posix(),
size="1GB",
size="1GiB",
recordable=recordable,
)

14
src/python/gem5/prebuilt/demo/x86_demo_board.py
View File

@@ -41,10 +41,10 @@ from ...utils.requires import requires
class X86DemoBoard(X86Board):
"""
This prebuilt X86 board is used for demonstration purposes. It simulates
an X86 3GHz quad-core system with a 2GB DDR3_1600 memory system. A
an X86 3GHz quad-core system with a 2GiB DDR3_1600 memory system. A
MESI_Two_Level cache hierarchy is set with an l1 data and instruction
cache, each 32kB with an associativity of 8, and a single bank l2 cache of
1MB with an associativity of 16.
cache, each 32KiB with an associativity of 8, and a single bank l2 cache of
1MiB with an associativity of 16.
**DISCLAIMER**: This board is solely for demonstration purposes. This board
is not known to be representative of any real-world system or produce
@@ -77,16 +77,16 @@ class X86DemoBoard(X86Board):
"real-world system. Use with caution."
)
memory = SingleChannelDDR3_1600(size="2GB")
memory = SingleChannelDDR3_1600(size="2GiB")
processor = SimpleProcessor(
cpu_type=CPUTypes.TIMING, isa=ISA.X86, num_cores=4
)
cache_hierarchy = MESITwoLevelCacheHierarchy(
l1d_size="32kB",
l1d_size="32KiB",
l1d_assoc=8,
l1i_size="32kB",
l1i_size="32KiB",
l1i_assoc=8,
l2_size="1MB",
l2_size="1MiB",
l2_assoc=16,
num_l2_banks=1,
)

18
src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
View File

@@ -77,7 +77,7 @@ def U74Memory():
"""
Memory for the U74 board.
DDR4 Subsystem with 16GB of memory.
DDR4 Subsystem with 16GiB of memory.
Starts at 0x80000000.
@@ -85,7 +85,7 @@ def U74Memory():
:return: ChanneledMemory
"""
memory = SingleChannelDDR4_2400("16GB")
memory = SingleChannelDDR4_2400("16GiB")
memory.set_memory_range(
[AddrRange(start=0x80000000, size=memory.get_size())]
)
@@ -121,7 +121,7 @@ class RISCVMatchedBoard(
:param clk_freq: The clock frequency of the system,
default: 1.2GHz
:param l2_size: The size of the L2 cache,
default: 2MB
default: 2MiB
:param is_fs: Whether the system is a full system or not,
default: False (SE Mode)
@@ -230,9 +230,9 @@ class RISCVMatchedBoard(
]
# PCI
self.bridge.ranges.append(AddrRange(0x2F000000, size="16MB"))
self.bridge.ranges.append(AddrRange(0x30000000, size="256MB"))
self.bridge.ranges.append(AddrRange(0x40000000, size="512MB"))
self.bridge.ranges.append(AddrRange(0x2F000000, size="16MiB"))
self.bridge.ranges.append(AddrRange(0x30000000, size="256MiB"))
self.bridge.ranges.append(AddrRange(0x40000000, size="512MiB"))
def _setup_pma(self) -> None:
"""Set the PMA devices on each core"""
@@ -243,9 +243,9 @@ class RISCVMatchedBoard(
]
# PCI
uncacheable_range.append(AddrRange(0x2F000000, size="16MB"))
uncacheable_range.append(AddrRange(0x30000000, size="256MB"))
uncacheable_range.append(AddrRange(0x40000000, size="512MB"))
uncacheable_range.append(AddrRange(0x2F000000, size="16MiB"))
uncacheable_range.append(AddrRange(0x30000000, size="256MiB"))
uncacheable_range.append(AddrRange(0x40000000, size="512MiB"))
# TODO: Not sure if this should be done per-core like in the example
for cpu in self.get_processor().get_cores():

4
src/python/gem5/prebuilt/riscvmatched/riscvmatched_cache.py
View File

@@ -79,7 +79,7 @@ class RISCVMatchedCacheHierarchy(
l2_size: str,
) -> None:
"""
:param l2_size: The size of the L2 Cache (e.g., "256kB").
:param l2_size: The size of the L2 Cache (e.g., "256KiB").
"""
AbstractClassicCacheHierarchy.__init__(self=self)
AbstractTwoLevelCacheHierarchy.__init__(
@@ -173,7 +173,7 @@ class RISCVMatchedCacheHierarchy(
data_latency=50,
response_latency=50,
mshrs=20,
size="1kB",
size="1KiB",
tgts_per_mshr=12,
addr_ranges=board.mem_ranges,
)