1 << x != (uint64_t)1 << x
dev/tsunami_cchip.cc:
fixed another problem with the interrupt code, should all work now
--HG--
extra : convert_revision : 1d9fe6081b6391e3e09f1c4a9380a30240fac6dc
This commit is contained in:
@@ -134,7 +134,6 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
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req->vaddr, req->size);
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Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6;
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uint64_t olddim;
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switch (req->size) {
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@@ -175,13 +174,17 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
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else
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number = 3;
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uint64_t bitvector;
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uint64_t olddim;
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uint64_t olddir;
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olddim = dim[number];
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olddir = dir[number];
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dim[number] = *(uint64_t*)data;
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dir[number] = dim[number] & drir;
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uint64_t bitvector;
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for(int x = 0; x < 64; x++)
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{
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bitvector = 1 << x;
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bitvector = (uint64_t)1 << x;
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// Figure out which bits have changed
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if ((dim[number] & bitvector) != (olddim & bitvector))
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{
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@@ -191,7 +194,8 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
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tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
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DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n");
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}
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else if (!(dir[number] & bitvector))
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else if ((olddir & bitvector) &&
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!(dir[number] & bitvector))
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{
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// The bit was set and now its now clear and
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// we were interrupting on that bit before
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@@ -244,7 +248,7 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
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void
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TsunamiCChip::postDRIR(uint32_t interrupt)
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{
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uint64_t bitvector = 0x1 << interrupt;
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uint64_t bitvector = (uint64_t)0x1 << interrupt;
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drir |= bitvector;
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for(int i=0; i < Tsunami::Max_CPUs; i++) {
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dir[i] = dim[i] & drir;
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@@ -259,7 +263,7 @@ TsunamiCChip::postDRIR(uint32_t interrupt)
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void
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TsunamiCChip::clearDRIR(uint32_t interrupt)
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{
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uint64_t bitvector = 0x1 << interrupt;
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uint64_t bitvector = (uint64_t)0x1 << interrupt;
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if (drir & bitvector)
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{
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drir &= ~bitvector;
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