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arm: Relax ordering for some uncacheable accesses

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We currently assume that all uncacheable memory accesses are strictly
ordered. Instead of always enforcing strict ordering, we now only
enforce it if the required memory type is device memory or strongly
ordered memory.
This commit is contained in:
Andreas Sandberg
2015-05-05 03:22:34 -04:00
parent 48281375ee
commit 706597f021
1 changed files with 7 additions and 1 deletions
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8
src/arch/arm/tlb.cc
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@@ -1076,7 +1076,13 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
setAttr(te->attributes);
if (te->nonCacheable)
req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
req->setFlags(Request::UNCACHEABLE);
// Require requests to be ordered if the request goes to
// strongly ordered or device memory (i.e., anything other
// than normal memory requires strict order).
if (te->mtype != TlbEntry::MemoryType::Normal)
req->setFlags(Request::STRICT_ORDER);
Addr pa = te->pAddr(vaddr);
req->setPaddr(pa);