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SPARC: Update stats for the call r15 as source change.

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This commit is contained in:
Gabe Black
2011-01-15 15:30:34 -08:00
parent 371603f12c
commit 6fb521faba
6 changed files with 1715 additions and 1714 deletions
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10
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
View File

@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 2 2010 15:11:52
M5 revision 9fcc50998835+ 7780+ default qtip tip set.patch qbase
M5 started Dec 3 2010 12:08:56
M5 executing on zizzer
M5 compiled Jan 15 2011 04:38:18
M5 revision 784f5d201f6e 7838 default callr15stats.patch tip qtip
M5 started Jan 15 2011 04:38:23
M5 executing on tater
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -43,4 +43,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 601459170500 because target called exit()
Exiting @ tick 601459117000 because target called exit()

364
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
View File

@@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 193964 # Simulator instruction rate (inst/s)
host_mem_usage 208068 # Number of bytes of host memory used
host_seconds 7246.73 # Real time elapsed on the host
host_tick_rate 82997346 # Simulator tick rate (ticks/s)
host_inst_rate 115319 # Simulator instruction rate (inst/s)
host_mem_usage 220936 # Number of bytes of host memory used
host_seconds 12188.85 # Real time elapsed on the host
host_tick_rate 49345009 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1405604152 # Number of instructions simulated
sim_seconds 0.601459 # Number of seconds simulated
sim_ticks 601459170500 # Number of ticks simulated
sim_ticks 601459117000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 98804477 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 100538318 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 98804472 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 100538302 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 5348297 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 105813048 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 105813048 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 105813027 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 105813027 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 86248929 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 21327804 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 21327805 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 1172142474 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 1172142381 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.270770 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.680117 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 418030495 35.66% 35.66% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 498323128 42.51% 78.18% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 52996990 4.52% 82.70% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 103673808 8.84% 91.54% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 418030405 35.66% 35.66% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 498323124 42.51% 78.18% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 52996988 4.52% 82.70% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 103673812 8.84% 91.54% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 32915552 2.81% 94.35% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 8294277 0.71% 95.06% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 8294276 0.71% 95.06% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 25634202 2.19% 97.25% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 10946218 0.93% 98.18% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 21327804 1.82% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 10946217 0.93% 98.18% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 21327805 1.82% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1172142474 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1172142381 # Number of insts commited each cycle
system.cpu.commit.COM:count 1489523295 # Number of instructions committed
system.cpu.commit.COM:loads 402512844 # Number of loads committed
system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
@@ -44,22 +44,22 @@ system.cpu.commit.COM:swp_count 0 # Nu
system.cpu.commit.branchMispredicts 5348297 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 219358956 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 219358890 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1405604152 # Number of Instructions Simulated
system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated
system.cpu.cpi 0.855802 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.855802 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 295702053 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14658.341236 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7465.553744 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_accesses 295702052 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14658.314544 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7465.427114 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 294883757 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 11994862000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 11994825500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002767 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 818296 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses 818295 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 604804 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1593836000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 1593801500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000722 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 213492 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses 213491 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 38142.857143 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35142.857143 # average SwapReq mshr miss latency
@@ -83,127 +83,127 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.001607 # m
system.cpu.dcache.WriteReq_mshr_misses 268065 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 955.149583 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 955.151567 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 462548869 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 15269.190131 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 10449.986812 # average overall mshr miss latency
system.cpu.dcache.demand_accesses 462548868 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 15269.181916 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 10449.936869 # average overall mshr miss latency
system.cpu.dcache.demand_hits 459964335 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 39463741045 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency 39463704545 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.005588 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2584534 # number of demand (read+write) misses
system.cpu.dcache.demand_misses 2584533 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2102977 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 5032264299 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 5032229799 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.001041 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 481557 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses 481556 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999859 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4095.424423 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 462548869 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 15269.190131 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 10449.986812 # average overall mshr miss latency
system.cpu.dcache.occ_blocks::0 4095.424477 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 462548868 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 15269.181916 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 10449.936869 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 459964335 # number of overall hits
system.cpu.dcache.overall_miss_latency 39463741045 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency 39463704545 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.005588 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2584534 # number of overall misses
system.cpu.dcache.overall_misses 2584533 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2102977 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 5032264299 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 5032229799 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.001041 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 481557 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses 481556 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 477468 # number of replacements
system.cpu.dcache.sampled_refs 481564 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 477467 # number of replacements
system.cpu.dcache.sampled_refs 481563 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.424423 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4095.424477 # Cycle average of tags in use
system.cpu.dcache.total_refs 459965654 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 132275000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 428419 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 393632662 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 1750743114 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 405697797 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 351108016 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 30410707 # Number of cycles decode is squashing
system.cpu.dcache.warmup_cycle 132267000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 428418 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 393632591 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 1750743071 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 405697785 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 351108006 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 30410701 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 21703388 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 105813048 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 173096808 # Number of cache lines fetched
system.cpu.fetch.Cycles 548235409 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1429410 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 1755979749 # Number of instructions fetch has processed
system.cpu.fetch.Branches 105813027 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 173096803 # Number of cache lines fetched
system.cpu.fetch.Cycles 548235394 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1429408 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 1755979705 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 6170644 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.087964 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 173096808 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 98804477 # Number of branches that fetch has predicted taken
system.cpu.fetch.icacheStallCycles 173096803 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 98804472 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.459766 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 1202552570 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::samples 1202552471 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.464003 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.699994 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 827414016 68.80% 68.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 82887160 6.89% 75.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 45822502 3.81% 79.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 22740112 1.89% 81.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 827413927 68.80% 68.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 82887157 6.89% 75.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 45822503 3.81% 79.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 22740108 1.89% 81.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 33832197 2.81% 84.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 32824408 2.73% 86.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 14992288 1.25% 88.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 32824411 2.73% 86.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 14992283 1.25% 88.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7935666 0.66% 88.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 134104221 11.15% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 134104219 11.15% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1202552570 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 173096808 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 35071.906355 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35057.573416 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 173095014 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 62919000 # number of ReadReq miss cycles
system.cpu.fetch.rateDist::total 1202552471 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 173096803 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 35063.545151 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35058.732612 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 173095009 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 62904000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1794 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 500 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 45364500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 45366000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 1294 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 133870.853828 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 133870.849961 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 173096808 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 35071.906355 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35057.573416 # average overall mshr miss latency
system.cpu.icache.demand_hits 173095014 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 62919000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_accesses 173096803 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 35063.545151 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35058.732612 # average overall mshr miss latency
system.cpu.icache.demand_hits 173095009 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 62904000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses
system.cpu.icache.demand_misses 1794 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 500 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 45364500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 45366000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 1294 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.509485 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1043.425077 # Average occupied blocks per context
system.cpu.icache.overall_accesses 173096808 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35071.906355 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35057.573416 # average overall mshr miss latency
system.cpu.icache.occ_blocks::0 1043.425085 # Average occupied blocks per context
system.cpu.icache.overall_accesses 173096803 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35063.545151 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35058.732612 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 173095014 # number of overall hits
system.cpu.icache.overall_miss_latency 62919000 # number of overall miss cycles
system.cpu.icache.overall_hits 173095009 # number of overall hits
system.cpu.icache.overall_miss_latency 62904000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses
system.cpu.icache.overall_misses 1794 # number of overall misses
system.cpu.icache.overall_mshr_hits 500 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 45364500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 45366000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 1294 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -211,39 +211,39 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 158 # number of replacements
system.cpu.icache.sampled_refs 1293 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1043.425077 # Cycle average of tags in use
system.cpu.icache.total_refs 173095014 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1043.425085 # Cycle average of tags in use
system.cpu.icache.total_refs 173095009 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 365772 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 89387990 # Number of branches executed
system.cpu.iew.EXEC:nop 102270124 # number of nop insts executed
system.cpu.idleCycles 365764 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 89387997 # Number of branches executed
system.cpu.iew.EXEC:nop 102270118 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.226826 # Inst execution rate
system.cpu.iew.EXEC:refs 590483047 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 169844843 # Number of stores executed
system.cpu.iew.EXEC:refs 590483044 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 169844841 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1212158392 # num instructions consuming a value
system.cpu.iew.WB:count 1472499117 # cumulative count of insts written-back
system.cpu.iew.WB:consumers 1212158273 # num instructions consuming a value
system.cpu.iew.WB:count 1472499084 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.958320 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1161635515 # num instructions producing a value
system.cpu.iew.WB:producers 1161635414 # num instructions producing a value
system.cpu.iew.WB:rate 1.224106 # insts written-back per cycle
system.cpu.iew.WB:sent 1473870782 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 5524570 # Number of branch mispredicts detected at execute
system.cpu.iew.WB:sent 1473870749 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 5524544 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 2522826 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 468104287 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 2975264 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 4542141 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 188277603 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 1708974065 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 420638204 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 6158152 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 1475771802 # Number of executed instructions
system.cpu.iew.iewDispLoadInsts 468104285 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 2975263 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 4542157 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 188277600 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 1708973999 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 420638203 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 6158150 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 1475771768 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 67057 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 9806 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 30410707 # Number of cycles IEW is squashing
system.cpu.iew.iewSquashCycles 30410701 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 130988 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 40442 # Number of times an access to memory failed due to the cache being blocked
@@ -253,15 +253,15 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 832421 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 264 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 65591443 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 21429461 # Number of stores squashed
system.cpu.iew.lsq.thread.0.squashedLoads 65591441 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 21429458 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 832421 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 648508 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 648482 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 4876062 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.168495 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.168495 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 884685461 59.70% 59.70% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 884685428 59.70% 59.70% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.70% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.70% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2618266 0.18% 59.87% # Type of FU issued
@@ -290,15 +290,15 @@ system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 59.87%
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 423845993 28.60% 88.48% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 170780234 11.52% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 423845992 28.60% 88.48% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 170780232 11.52% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 1481929954 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 3245028 # FU busy when requested
system.cpu.iq.ISSUE:FU_type_0::total 1481929918 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 3245029 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.002190 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 213199 6.57% 6.57% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 213200 6.57% 6.57% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 6.57% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.57% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 176159 5.43% 12.00% # attempts to use FU when none available
@@ -331,31 +331,31 @@ system.cpu.iq.ISSUE:fu_full::MemRead 2529947 77.96% 89.96% # at
system.cpu.iq.ISSUE:fu_full::MemWrite 325723 10.04% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 1202552570 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 1202552471 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.232320 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.127769 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 320558018 26.66% 26.66% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 511599251 42.54% 69.20% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 219311196 18.24% 87.44% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 94899600 7.89% 95.33% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 39949792 3.32% 98.65% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 10701863 0.89% 99.54% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 5167479 0.43% 99.97% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 226814 0.02% 99.99% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 320557937 26.66% 26.66% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 511599256 42.54% 69.20% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 219311183 18.24% 87.44% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 94899588 7.89% 95.33% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 39949785 3.32% 98.65% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 10701869 0.89% 99.54% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 5167481 0.43% 99.97% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 226815 0.02% 99.99% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 138557 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 1202552570 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 1202552471 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.231946 # Inst issue rate
system.cpu.iq.iqInstsAdded 1603628020 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 1481929954 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 3075921 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 200595245 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqInstsAdded 1603627961 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 1481929918 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 3075920 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 200595189 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 67507 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 832250 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 279093413 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 832249 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 279093354 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 268080 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.623615 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31319.356706 # average ReadExReq mshr miss latency
@@ -366,87 +366,87 @@ system.cpu.l2cache.ReadExReq_misses 60470 # nu
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893881500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225567 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 60470 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 214778 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34036.356888 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.002969 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_accesses 214777 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34036.417352 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.032810 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 181098 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1146344500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.156813 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 33680 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1044248500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156813 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 33680 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 428419 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 428419 # number of Writeback hits
system.cpu.l2cache.ReadReq_miss_latency 1146312500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.156809 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 33679 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1044218500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156809 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 33679 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 428418 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 428418 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 5.114590 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 5.114484 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 482858 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34274.811471 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31206.903877 # average overall mshr miss latency
system.cpu.l2cache.demand_accesses 482857 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34274.835633 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31206.916696 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 388708 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 3226973500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.194985 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 94150 # number of demand (read+write) misses
system.cpu.l2cache.demand_miss_latency 3226941500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.194983 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 94149 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 2938130000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.194985 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 94150 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 2938100000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.194983 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 94149 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.060598 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.478382 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1985.675951 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15675.618394 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 482858 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34274.811471 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31206.903877 # average overall mshr miss latency
system.cpu.l2cache.occ_blocks::0 1985.676117 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15675.618625 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 482857 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34274.835633 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31206.916696 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 388708 # number of overall hits
system.cpu.l2cache.overall_miss_latency 3226973500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.194985 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 94150 # number of overall misses
system.cpu.l2cache.overall_miss_latency 3226941500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.194983 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 94149 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 2938130000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.194985 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 94150 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 2938100000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.194983 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 94149 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 75916 # number of replacements
system.cpu.l2cache.sampled_refs 91430 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 91428 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 17661.294345 # Cycle average of tags in use
system.cpu.l2cache.total_refs 467627 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 17661.294741 # Cycle average of tags in use
system.cpu.l2cache.total_refs 467607 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 59275 # number of writebacks
system.cpu.memDep0.conflictingLoads 406523724 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 165665166 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 468104287 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 188277603 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 1202918342 # number of cpu cycles simulated
system.cpu.memDep0.insertedLoads 468104285 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 188277600 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 1202918235 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 123850375 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1244770452 # Number of HB maps that are committed
system.cpu.rename.RENAME:FullRegisterEvents 28358883 # Number of times there has been no free registers
system.cpu.rename.RENAME:IQFullEvents 134234499 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 443701080 # Number of cycles rename is idle
system.cpu.rename.RENAME:IdleCycles 443701065 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 41034727 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 2926118072 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 1732032872 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 1445195761 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 329589448 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 30410707 # Number of cycles rename is squashing
system.cpu.rename.RENAME:RenameLookups 2924510246 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 1732032824 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 1445195719 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 329589441 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 30410701 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 217220623 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 200425309 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 57780337 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:UndoneMaps 200425267 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 57780266 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 3037077 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 385268433 # count of insts added to the skid buffer
system.cpu.rename.RENAME:skidInsts 385268446 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 3036332 # count of temporary serializing insts renamed
system.cpu.timesIdled 11396 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls

10
tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
View File

@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 2 2010 15:11:52
M5 revision 9fcc50998835+ 7780+ default qtip tip set.patch qbase
M5 started Dec 2 2010 19:10:47
M5 executing on zizzer
M5 compiled Jan 15 2011 04:38:18
M5 revision 784f5d201f6e 7838 default callr15stats.patch tip qtip
M5 started Jan 15 2011 04:38:23
M5 executing on tater
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -23,4 +23,4 @@ LDTX: Passed
LDTW: Passed
STTW: Passed
Done
Exiting @ tick 18731500 because target called exit()
Exiting @ tick 18656000 because target called exit()

522
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
View File

@@ -1,64 +1,64 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 90431 # Simulator instruction rate (inst/s)
host_mem_usage 203888 # Number of bytes of host memory used
host_seconds 0.16 # Real time elapsed on the host
host_tick_rate 117038227 # Simulator tick rate (ticks/s)
host_inst_rate 46971 # Simulator instruction rate (inst/s)
host_mem_usage 216748 # Number of bytes of host memory used
host_seconds 0.31 # Real time elapsed on the host
host_tick_rate 60590117 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 14449 # Number of instructions simulated
sim_seconds 0.000019 # Number of seconds simulated
sim_ticks 18731500 # Number of ticks simulated
sim_ticks 18656000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 2701 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 5096 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 2698 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 5085 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 725 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 5196 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 5196 # Number of BP lookups
system.cpu.BPredUnit.condIncorrect 714 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 5172 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 5172 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 3359 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 84 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 27718 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.547478 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.185032 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 27579 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.550237 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.187070 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 19937 71.93% 71.93% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 4515 16.29% 88.22% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 1459 5.26% 93.48% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 767 2.77% 96.25% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 374 1.35% 97.60% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 256 0.92% 98.52% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 289 1.04% 99.56% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 19793 71.77% 71.77% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 4521 16.39% 88.16% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 1461 5.30% 93.46% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 765 2.77% 96.23% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 373 1.35% 97.59% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 256 0.93% 98.51% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 289 1.05% 99.56% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 37 0.13% 99.70% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 84 0.30% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 27718 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 27579 # Number of insts commited each cycle
system.cpu.commit.COM:count 15175 # Number of instructions committed
system.cpu.commit.COM:loads 2226 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 3674 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 725 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 714 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 5217 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 5133 # The number of squashed insts skipped by commit
system.cpu.committedInsts 14449 # Number of Instructions Simulated
system.cpu.committedInsts_total 14449 # Number of Instructions Simulated
system.cpu.cpi 2.592844 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.592844 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 2789 # number of ReadReq accesses(hits+misses)
system.cpu.cpi 2.582393 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.582393 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 2777 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 33620.967742 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35563.492063 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 2665 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits 2653 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4169000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.044460 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate 0.044653 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 124 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 61 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 2240500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.022589 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate 0.022686 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 63 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
@@ -75,167 +75,167 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # m
system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 25.376712 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 25.294521 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 4231 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses 4219 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 35362.781955 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35722.602740 # average overall mshr miss latency
system.cpu.dcache.demand_hits 3699 # number of demand (read+write) hits
system.cpu.dcache.demand_hits 3687 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 18813000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.125739 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate 0.126096 # miss rate for demand accesses
system.cpu.dcache.demand_misses 532 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 386 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 5215500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.034507 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate 0.034605 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.024963 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 102.247340 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 4231 # number of overall (read+write) accesses
system.cpu.dcache.occ_%::0 0.024937 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 102.143173 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 4219 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 35362.781955 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35722.602740 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 3699 # number of overall hits
system.cpu.dcache.overall_hits 3687 # number of overall hits
system.cpu.dcache.overall_miss_latency 18813000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.125739 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate 0.126096 # miss rate for overall accesses
system.cpu.dcache.overall_misses 532 # number of overall misses
system.cpu.dcache.overall_mshr_hits 386 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 5215500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.034507 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate 0.034605 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 102.247340 # Cycle average of tags in use
system.cpu.dcache.total_refs 3705 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 102.143173 # Cycle average of tags in use
system.cpu.dcache.total_refs 3693 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 7118 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 23678 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 13190 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 7286 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 1191 # Number of cycles decode is squashing
system.cpu.decode.DECODE:BlockedCycles 7077 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 23586 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 13112 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 7266 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 1178 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 107 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 5196 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 4112 # Number of cache lines fetched
system.cpu.fetch.Cycles 11672 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.Branches 5172 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 4077 # Number of cache lines fetched
system.cpu.fetch.Cycles 11611 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 385 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 24093 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 837 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.138693 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 4112 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 2701 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.643097 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 28892 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.833899 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.950141 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.Insts 23982 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 826 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.138611 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 4077 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 2698 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.642725 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 28740 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.834447 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.949360 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 21359 73.93% 73.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3597 12.45% 86.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 580 2.01% 88.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 513 1.78% 90.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 668 2.31% 92.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 530 1.83% 94.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 244 0.84% 95.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 197 0.68% 95.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1204 4.17% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 21234 73.88% 73.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3581 12.46% 86.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 587 2.04% 88.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 509 1.77% 90.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 664 2.31% 92.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 529 1.84% 94.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 246 0.86% 95.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 197 0.69% 95.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1193 4.15% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 28892 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 4112 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 34753.073770 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34880.281690 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 3624 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 16959500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.118677 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 488 # number of ReadReq misses
system.cpu.fetch.rateDist::total 28740 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 4077 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 34819.301848 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34975.988701 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 3590 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 16957000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.119451 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 487 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 133 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 12382500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.086333 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 355 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency 12381500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.086829 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 354 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 10.237288 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 10.141243 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 4112 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 34753.073770 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34880.281690 # average overall mshr miss latency
system.cpu.icache.demand_hits 3624 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 16959500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.118677 # miss rate for demand accesses
system.cpu.icache.demand_misses 488 # number of demand (read+write) misses
system.cpu.icache.demand_accesses 4077 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 34819.301848 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34975.988701 # average overall mshr miss latency
system.cpu.icache.demand_hits 3590 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 16957000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.119451 # miss rate for demand accesses
system.cpu.icache.demand_misses 487 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 12382500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.086333 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 355 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_miss_latency 12381500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.086829 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 354 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.099925 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 204.645792 # Average occupied blocks per context
system.cpu.icache.overall_accesses 4112 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 34753.073770 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34880.281690 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.099779 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 204.347725 # Average occupied blocks per context
system.cpu.icache.overall_accesses 4077 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 34819.301848 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34975.988701 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 3624 # number of overall hits
system.cpu.icache.overall_miss_latency 16959500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.118677 # miss rate for overall accesses
system.cpu.icache.overall_misses 488 # number of overall misses
system.cpu.icache.overall_hits 3590 # number of overall hits
system.cpu.icache.overall_miss_latency 16957000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.119451 # miss rate for overall accesses
system.cpu.icache.overall_misses 487 # number of overall misses
system.cpu.icache.overall_mshr_hits 133 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 12382500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.086333 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 355 # number of overall MSHR misses
system.cpu.icache.overall_mshr_miss_latency 12381500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.086829 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 354 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.sampled_refs 354 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 204.645792 # Cycle average of tags in use
system.cpu.icache.total_refs 3624 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 204.347725 # Cycle average of tags in use
system.cpu.icache.total_refs 3590 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 8572 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 3845 # Number of branches executed
system.cpu.iew.EXEC:nop 1083 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.470131 # Inst execution rate
system.cpu.iew.EXEC:refs 4644 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 1769 # Number of stores executed
system.cpu.idleCycles 8573 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 3856 # Number of branches executed
system.cpu.iew.EXEC:nop 1087 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.470989 # Inst execution rate
system.cpu.iew.EXEC:refs 4619 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 1763 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 9394 # num instructions consuming a value
system.cpu.iew.WB:count 17150 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.855972 # average fanout of values written-back
system.cpu.iew.WB:consumers 9338 # num instructions consuming a value
system.cpu.iew.WB:count 17128 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.855858 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 8041 # num instructions producing a value
system.cpu.iew.WB:rate 0.457773 # insts written-back per cycle
system.cpu.iew.WB:sent 17335 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 821 # Number of branch mispredicts detected at execute
system.cpu.iew.WB:producers 7992 # num instructions producing a value
system.cpu.iew.WB:rate 0.459036 # insts written-back per cycle
system.cpu.iew.WB:sent 17304 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 800 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 147 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 3080 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 569 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 401 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 1935 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 20414 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 2875 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 481 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 17613 # Number of executed instructions
system.cpu.iew.iewDispLoadInsts 3058 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 566 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 420 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 1925 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 20324 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 2856 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 465 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 17574 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 1191 # Number of cycles IEW is squashing
system.cpu.iew.iewSquashCycles 1178 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
@@ -245,109 +245,109 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 54 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 854 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 487 # Number of stores squashed
system.cpu.iew.lsq.thread.0.squashedLoads 832 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 477 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 54 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 582 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 239 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.385677 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.385677 # IPC: Total IPC of All Threads
system.cpu.iew.predictedNotTakenIncorrect 560 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 240 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.387238 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.387238 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 13329 73.67% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 73.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 2941 16.25% 89.92% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1824 10.08% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 13302 73.74% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 73.74% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 2921 16.19% 89.93% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1816 10.07% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 18094 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 123 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.006798 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:FU_type_0::total 18039 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 125 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.006929 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 26 21.14% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 29 23.58% 44.72% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 68 55.28% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 28 22.40% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 29 23.20% 45.60% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 68 54.40% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 28892 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.626263 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.192032 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 28740 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.627662 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.192852 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 20022 69.30% 69.30% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 4253 14.72% 84.02% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 1909 6.61% 90.63% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 1729 5.98% 96.61% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 432 1.50% 98.11% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 282 0.98% 99.08% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 171 0.59% 99.67% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 19886 69.19% 69.19% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 4262 14.83% 84.02% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 1894 6.59% 90.61% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 1722 5.99% 96.60% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 431 1.50% 98.10% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 279 0.97% 99.07% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 172 0.60% 99.67% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 80 0.28% 99.95% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 14 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 28892 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.482970 # Inst issue rate
system.cpu.iq.iqInstsAdded 18762 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 18094 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 569 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 4139 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 76 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 94 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 3725 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.ISSUE:issued_per_cycle::total 28740 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.483451 # Inst issue rate
system.cpu.iq.iqInstsAdded 18671 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 18039 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 566 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 4088 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 81 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 3603 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34596.385542 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31451.807229 # average ReadExReq mshr miss latency
@@ -357,16 +357,16 @@ system.cpu.l2cache.ReadExReq_misses 83 # nu
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2610500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 418 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34234.299517 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31008.454106 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_accesses 417 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34314.769976 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31082.324455 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 14173000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.990431 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 414 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 12837500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990431 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 414 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_miss_latency 14172000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.990408 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 413 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 12837000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990408 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 413 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.009685 # Average number of references to valid blocks.
@@ -375,63 +375,63 @@ system.cpu.l2cache.blocked::no_targets 0 # nu
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 501 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34294.768612 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31082.494970 # average overall mshr miss latency
system.cpu.l2cache.demand_accesses 500 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34361.895161 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31144.153226 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 17044500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.992016 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
system.cpu.l2cache.demand_miss_latency 17043500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.992000 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 496 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 15448000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.992016 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 497 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 15447500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.992000 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 496 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.007292 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 238.958608 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 501 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34294.768612 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31082.494970 # average overall mshr miss latency
system.cpu.l2cache.occ_%::0 0.007282 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 238.619810 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 500 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34361.895161 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31144.153226 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 4 # number of overall hits
system.cpu.l2cache.overall_miss_latency 17044500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.992016 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 497 # number of overall misses
system.cpu.l2cache.overall_miss_latency 17043500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.992000 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 496 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 15448000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.992016 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 497 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 15447500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.992000 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 496 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 238.958608 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 238.619810 # Cycle average of tags in use
system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 3080 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1935 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 37464 # number of cpu cycles simulated
system.cpu.memDep0.insertedLoads 3058 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1925 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 37313 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 254 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed
system.cpu.rename.RENAME:IdleCycles 13649 # Number of cycles rename is idle
system.cpu.rename.RENAME:IdleCycles 13569 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 112 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 40984 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 21894 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 19600 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 7060 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 1191 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 422 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 5768 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 6316 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 622 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 2701 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 587 # count of temporary serializing insts renamed
system.cpu.rename.RENAME:RenameLookups 40450 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 21815 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 19528 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 7042 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 1178 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 421 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 5696 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 6276 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 617 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 2691 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 583 # count of temporary serializing insts renamed
system.cpu.timesIdled 183 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls

54
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
View File

@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 2 2010 15:11:52
M5 revision 9fcc50998835+ 7780+ default qtip tip set.patch qbase
M5 started Dec 2 2010 19:11:11
M5 executing on zizzer
M5 compiled Jan 15 2011 04:38:18
M5 revision 784f5d201f6e 7838 default callr15stats.patch tip qtip
M5 started Jan 15 2011 04:38:23
M5 executing on tater
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -36,17 +36,17 @@ Iteration 2 completed
Iteration 3 completed
[Iteration 4, Thread 2] Got lock
[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 4, Thread 1] Got lock
[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1
[Iteration 4, Thread 3] Got lock
[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3
[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 4, Thread 1] Got lock
[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
Iteration 4 completed
[Iteration 5, Thread 3] Got lock
[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 5, Thread 1] Got lock
[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1
[Iteration 5, Thread 2] Got lock
[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2
[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
[Iteration 5, Thread 1] Got lock
[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
Iteration 5 completed
[Iteration 6, Thread 1] Got lock
[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1
@@ -55,33 +55,33 @@ Iteration 5 completed
[Iteration 6, Thread 2] Got lock
[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2
Iteration 6 completed
[Iteration 7, Thread 1] Got lock
[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 7, Thread 2] Got lock
[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2
[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 7, Thread 1] Got lock
[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
[Iteration 7, Thread 3] Got lock
[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
Iteration 7 completed
[Iteration 8, Thread 1] Got lock
[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 8, Thread 3] Got lock
[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
[Iteration 8, Thread 2] Got lock
[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2
[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 8, Thread 3] Got lock
[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 8, Thread 1] Got lock
[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
Iteration 8 completed
[Iteration 9, Thread 2] Got lock
[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 9, Thread 3] Got lock
[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 9, Thread 1] Got lock
[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1
[Iteration 9, Thread 2] Got lock
[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2
Iteration 9 completed
[Iteration 10, Thread 2] Got lock
[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 10, Thread 3] Got lock
[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 10, Thread 2] Got lock
[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
[Iteration 10, Thread 1] Got lock
[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
Iteration 10 completed
PASSED :-)
Exiting @ tick 117665000 because target called exit()
Exiting @ tick 117496500 because target called exit()

2469
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
View File

File diff suppressed because it is too large Load Diff