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arch-arm: Add missing outer-shareable TLBIs to the list (#1147)

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Those were not part of the performTlbi switch and simulation was
therefore panicking when they were encountered

Change-Id: Ifbe0b89e45539df4abc147ac5970b0caf0d9dfdc

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Giacomo Travaglini
2024-05-21 04:24:45 +02:00
committed by GitHub
parent 13924336b1
commit 6f4ba0b422
1 changed files with 4 additions and 1 deletions
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5
src/arch/arm/insts/misc64.cc
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2011-2013,2017-2023 Arm Limited
* Copyright (c) 2011-2013,2017-2024 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -586,6 +586,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
return;
}
case MISCREG_TLBI_VALE1IS:
case MISCREG_TLBI_VALE1OS:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
auto asid = asid_16bits ? bits(value, 63, 48) :
@@ -935,6 +936,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
return;
}
case MISCREG_TLBI_RIPAS2E1IS:
case MISCREG_TLBI_RIPAS2E1OS:
{
if (EL2Enabled(tc)) {
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
@@ -963,6 +965,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
return;
}
case MISCREG_TLBI_RIPAS2LE1IS:
case MISCREG_TLBI_RIPAS2LE1OS:
{
if (EL2Enabled(tc)) {
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);