arch-arm: inform bootloader of kernel position with a register

Before the commit, the bootloader had a hardcoded entry point that it
would jump to.

However, the Linux kernel arm64 v5.8 forced us to change the kernel
entry point because the required memory alignment has changed at:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
commit/?h=v5.8&id=cfa7ede20f133cc81cef01dc3a516dda3a9721ee

Therefore the only way to have a single bootloader that boots both
pre-v5.8 and post-v5.8 kernels is to pass that information from gem5
to the bootloader, which we do in this patch via registers.

This approach was already used by the 32-bit bootloader, which passed
that value via r3, and we try to use the same register x3 in 64-bit.

Since we are now passing this information, the this patch also removes
the hardcoding of DTB and cpu-release-addr, and also passes those
values via registers.

We store the cpu-release-addr in x5 as that value appears to have a
function similar to flags_addr, which is used only in 32-bit arm and
gets stored in r5.

This commit renames atags_addr to dtb_addr, since both are mutually
exclusive, and serve a similar purpose, DTB being the newer recommended
approach.

Similarly, flags_addr is renamed to cpu_release_addr, and it is moved
from ArmSystem into ArmFsWorkload, since it is not an intrinsic system
property, and should be together with dtb_addr instead.

Before this commit, flags_addr was being set from FSConfig.py and
configs/example/arm/devices.py to self.realview.realview_io.pio_addr
+ 0x30. This commit moves that logic into RealView.py instead, and
sets the flags address 8 bytes before the start of the DTB address.

JIRA: https://gem5.atlassian.net/browse/GEM5-787
Change-Id: If70bea9690be04b84e6040e256a9b03e46710e10
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35076
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

system/arm/bootloader/arm64/boot.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -40,6 +40,14 @@
 
         .globl	_start
 _start:
+        /* Save some values initialized by gem5. */
+        /* DTB address. */
+        mov x21, x0
+        /* Kernel entry point. */
+        mov x20, x3
+        /* cpu-release-addr. */
+        mov x22, x5
+
         /*
          * EL3 initialisation
          */
@@ -153,8 +161,19 @@ start_ns:
          * Secondary CPUs
          */
 1:	wfe
-        ldr	x4, =PHYS_OFFSET + 0xfff8
-        ldr     x4, [x4]
+        /* The Linux kernel v5.8 and older writes the entry point address
+         * of the secondary CPUs to this address, and does a SEV, waking up
+         * the secondary CPUs.
+         *
+         * gem5 informs the kernel the desired address via cpu-release-addr
+         * of the DTB.
+         *
+         * When this is first reached immediately after the bootloader starts,
+         * the value at that address must be 0, which is the default memory
+         * value set by gem5 for otherwise uninitialized memory, leading to
+         * WFE.
+         */
+        ldr x4, [x22]
         cbz	x4, 1b
         br	x4				// branch to the given address
 
@@ -180,9 +199,13 @@ start_ns:
         /*
          * Primary CPU
          */
-        ldr	x0, =PHYS_OFFSET + 0x8000000	 // device tree blob
-        ldr     x6, =PHYS_OFFSET + 0x80000       // kernel start address
-        br	x6
+        // The kernel boot protocol specifies that the DTB address is placed
+        // in x0.
+        // https://github.com/torvalds/linux/blob/v5.7/Documentation/arm64/
+        // booting.rst#4-call-the-kernel-image
+        mov x0, x21
+        // Jump into the kernel entry point.
+        br x20
 
         .ltorg