arch-arm: inform bootloader of kernel position with a register
Before the commit, the bootloader had a hardcoded entry point that it would jump to. However, the Linux kernel arm64 v5.8 forced us to change the kernel entry point because the required memory alignment has changed at: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/ commit/?h=v5.8&id=cfa7ede20f133cc81cef01dc3a516dda3a9721ee Therefore the only way to have a single bootloader that boots both pre-v5.8 and post-v5.8 kernels is to pass that information from gem5 to the bootloader, which we do in this patch via registers. This approach was already used by the 32-bit bootloader, which passed that value via r3, and we try to use the same register x3 in 64-bit. Since we are now passing this information, the this patch also removes the hardcoding of DTB and cpu-release-addr, and also passes those values via registers. We store the cpu-release-addr in x5 as that value appears to have a function similar to flags_addr, which is used only in 32-bit arm and gets stored in r5. This commit renames atags_addr to dtb_addr, since both are mutually exclusive, and serve a similar purpose, DTB being the newer recommended approach. Similarly, flags_addr is renamed to cpu_release_addr, and it is moved from ArmSystem into ArmFsWorkload, since it is not an intrinsic system property, and should be together with dtb_addr instead. Before this commit, flags_addr was being set from FSConfig.py and configs/example/arm/devices.py to self.realview.realview_io.pio_addr + 0x30. This commit moves that logic into RealView.py instead, and sets the flags address 8 bytes before the start of the DTB address. JIRA: https://gem5.atlassian.net/browse/GEM5-787 Change-Id: If70bea9690be04b84e6040e256a9b03e46710e10 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35076 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2012 ARM Limited
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* Copyright (c) 2012, 2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@@ -40,6 +40,14 @@
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.globl _start
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_start:
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/* Save some values initialized by gem5. */
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/* DTB address. */
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mov x21, x0
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/* Kernel entry point. */
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mov x20, x3
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/* cpu-release-addr. */
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mov x22, x5
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/*
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* EL3 initialisation
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*/
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@@ -153,8 +161,19 @@ start_ns:
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* Secondary CPUs
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*/
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1: wfe
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ldr x4, =PHYS_OFFSET + 0xfff8
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ldr x4, [x4]
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/* The Linux kernel v5.8 and older writes the entry point address
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* of the secondary CPUs to this address, and does a SEV, waking up
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* the secondary CPUs.
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*
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* gem5 informs the kernel the desired address via cpu-release-addr
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* of the DTB.
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*
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* When this is first reached immediately after the bootloader starts,
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* the value at that address must be 0, which is the default memory
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* value set by gem5 for otherwise uninitialized memory, leading to
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* WFE.
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*/
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ldr x4, [x22]
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cbz x4, 1b
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br x4 // branch to the given address
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@@ -180,9 +199,13 @@ start_ns:
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/*
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* Primary CPU
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*/
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ldr x0, =PHYS_OFFSET + 0x8000000 // device tree blob
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ldr x6, =PHYS_OFFSET + 0x80000 // kernel start address
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br x6
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// The kernel boot protocol specifies that the DTB address is placed
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// in x0.
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// https://github.com/torvalds/linux/blob/v5.7/Documentation/arm64/
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// booting.rst#4-call-the-kernel-image
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mov x0, x21
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// Jump into the kernel entry point.
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br x20
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.ltorg
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@@ -34,11 +34,7 @@ BUILDDIR = .
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DESTDIR = $(error Please set DESTDIR to wanted installation directory)
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CFLAGS = -march=armv8-a
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CPPFLAGS = -DPHYS_OFFSET=0x80000000 \
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-DUART_BASE=0x1c090000 -DSYSREGS_BASE=0x1c010000 \
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-Dkernel=0x80080000 \
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-Dmbox=0x8000fff8 -Ddtb=0x80000100
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CPPFLAGS = -DUART_BASE=0x1c090000 -DSYSREGS_BASE=0x1c010000
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LDFLAGS = -N -Ttext 0x00000010 -static
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.PHONY: all clean install mkdir
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