Misc fixes.

src/cpu/o3/alpha_dyn_inst_impl.hh:
    Consolidate these calls into one.
src/cpu/o3/commit_impl.hh:
    Include checker only if it's being used.
src/cpu/o3/fetch_impl.hh:
    Do not deallocate request if it's a squashed response that was received.
src/cpu/o3/lsq_unit.hh:
    Add in comment.
src/cpu/o3/lsq_unit_impl.hh:
    Only include checker if it's being used.

--HG--
extra : convert_revision : aae0bf1e19baae90f1e61d41191548612bbb3be6
This commit is contained in:
Kevin Lim
2006-06-22 18:09:31 -04:00
parent 9ca5427c03
commit 6e95bcd333
5 changed files with 11 additions and 12 deletions

View File

@@ -102,15 +102,7 @@ template <class Impl>
Fault
AlphaDynInst<Impl>::completeAcc(Packet *pkt)
{
if (this->isLoad()) {
this->fault = this->staticInst->completeAcc(pkt, this,
this->traceData);
} else if (this->isStore()) {
this->fault = this->staticInst->completeAcc(pkt, this,
this->traceData);
} else {
panic("Unknown type!");
}
this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
return this->fault;
}

View File

@@ -36,11 +36,14 @@
#include "base/loader/symtab.hh"
#include "base/timebuf.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/exetrace.hh"
#include "cpu/o3/commit.hh"
#include "cpu/o3/thread_state.hh"
#if USE_CHECKER
#include "cpu/checker/cpu.hh"
#endif
using namespace std;
template <class Impl>

View File

@@ -357,7 +357,6 @@ DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
++fetchIcacheSquashes;
delete pkt->req;
delete pkt;
memReq[tid] = NULL;
return;
}

View File

@@ -128,6 +128,8 @@ class LSQUnit {
/** Writes back stores. */
void writebackStores();
/** Completes the data access that has been returned from the
* memory system. */
void completeDataAccess(PacketPtr pkt);
/** Clears all the entries in the LQ. */

View File

@@ -31,12 +31,15 @@
#include "config/use_checker.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/o3/lsq_unit.hh"
#include "base/str.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#if USE_CHECKER
#include "cpu/checker/cpu.hh"
#endif
template<class Impl>
LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
LSQUnit *lsq_ptr)