ARM: Implement the bkpt instruction.

src/arch/arm/isa/formats/data.isa

@@ -1167,7 +1167,7 @@ def format Thumb16Misc() {{
                                   true, true, regList);
             }
           case 0xe:
-            return new WarnUnimplemented("bkpt", machInst);
+            return new BkptInst(machInst);
           case 0xf:
             if (bits(machInst, 3, 0) != 0)
                 return new ItInst(machInst);

src/arch/arm/isa/insts/misc.isa

@@ -456,6 +456,12 @@ let {{
     decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
     exec_output += PredOpExecute.subst(usada8Iop)
 
+    bkptIop = InstObjParams("bkpt", "BkptInst", "ArmStaticInst",
+            "return new PrefetchAbort(PC, ArmFault::DebugEvent);")
+    header_output += BasicDeclare.subst(bkptIop)
+    decoder_output += BasicConstructor.subst(bkptIop)
+    exec_output += BasicExecute.subst(bkptIop)
+
     nopIop = InstObjParams("nop", "NopInst", "PredOp", \
             { "code" : "", "predicate_test" : predicateTest })
     header_output += BasicDeclare.subst(nopIop)

src/arch/arm/isa/operands.isa

@@ -179,6 +179,7 @@ def operands {{
     'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2),
     'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 2),
     'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 2),
+    'PC': ('PC', 'ud', None, None, 2),
     'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
             readNPC, writeNPC),
     'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,