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Merge ktlim@zizzer:/bk/newmem

Browse Source 
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

configs/test/test.py:
    Hand merge.

--HG--
extra : convert_revision : e3fce9cf50a65a9400cd3ec887b13e4765274ec2
This commit is contained in:
Kevin Lim
2006-07-12 17:21:25 -04:00
parent bbfe1db6b3 6f81ae5cad
commit 6dfaf06edf
14 changed files with 241 additions and 248 deletions
Download Patch File Download Diff File Expand all files Collapse all files

214
configs/test/fs.py
View File

@@ -3,10 +3,15 @@ import optparse, os, sys
import m5
from m5.objects import *
from SysPaths import *
from FullO3Config import *
parser = optparse.OptionParser()
parser.add_option("-d", "--detailed", action="store_true")
parser.add_option("-t", "--timing", action="store_true")
parser.add_option("-m", "--maxtick", type="int")
parser.add_option("--dual", help="Run full system using dual systems",
action="store_true")
(options, args) = parser.parse_args()
@@ -19,179 +24,52 @@ test_base = os.path.dirname(__file__)
linux_image = env.get('LINUX_IMAGE', disk('linux-latest.img'))
class IdeControllerPciData(PciConfigData):
VendorID = 0x8086
DeviceID = 0x7111
Command = 0x0
Status = 0x280
Revision = 0x0
ClassCode = 0x01
SubClassCode = 0x01
ProgIF = 0x85
BAR0 = 0x00000001
BAR1 = 0x00000001
BAR2 = 0x00000001
BAR3 = 0x00000001
BAR4 = 0x00000001
BAR5 = 0x00000001
InterruptLine = 0x1f
InterruptPin = 0x01
BAR0Size = '8B'
BAR1Size = '4B'
BAR2Size = '8B'
BAR3Size = '4B'
BAR4Size = '16B'
class CowIdeDisk(IdeDisk):
image = CowDiskImage(child=RawDiskImage(read_only=True),
read_only=False)
class SinicPciData(PciConfigData):
VendorID = 0x1291
DeviceID = 0x1293
Status = 0x0290
SubClassCode = 0x00
ClassCode = 0x02
ProgIF = 0x00
BAR0 = 0x00000000
BAR1 = 0x00000000
BAR2 = 0x00000000
BAR3 = 0x00000000
BAR4 = 0x00000000
BAR5 = 0x00000000
MaximumLatency = 0x34
MinimumGrant = 0xb0
InterruptLine = 0x1e
InterruptPin = 0x01
BAR0Size = '64kB'
class NSGigEPciData(PciConfigData):
VendorID = 0x100B
DeviceID = 0x0022
Status = 0x0290
SubClassCode = 0x00
ClassCode = 0x02
ProgIF = 0x00
BAR0 = 0x00000001
BAR1 = 0x00000000
BAR2 = 0x00000000
BAR3 = 0x00000000
BAR4 = 0x00000000
BAR5 = 0x00000000
MaximumLatency = 0x34
MinimumGrant = 0xb0
InterruptLine = 0x1e
InterruptPin = 0x01
BAR0Size = '256B'
BAR1Size = '4kB'
class LinuxRootDisk(IdeDisk):
raw_image = RawDiskImage(image_file=linux_image, read_only=True)
image = CowDiskImage(child=Parent.raw_image, read_only=False)
class LinuxSwapDisk(IdeDisk):
raw_image = RawDiskImage(image_file = disk('linux-bigswap2.img'),
read_only=True)
image = CowDiskImage(child = Parent.raw_image, read_only=False)
class SpecwebFilesetDisk(IdeDisk):
raw_image = RawDiskImage(image_file = disk('specweb-fileset.img'),
read_only=True)
image = CowDiskImage(child = Parent.raw_image, read_only=False)
def childImage(self, ci):
self.image.child.image_file = ci
class BaseTsunami(Tsunami):
cchip = TsunamiCChip(pio_addr=0x801a0000000)
pchip = TsunamiPChip(pio_addr=0x80180000000)
pciconfig = PciConfigAll()
fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
fake_ppc = IsaFake(pio_addr=0x801fc0003bc)
fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
fake_ata1 = IsaFake(pio_addr=0x801fc000170)
fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
io = TsunamiIO(pio_addr=0x801fc000000)
uart = Uart8250(pio_addr=0x801fc0003f8)
ethernet = NSGigE(configdata=NSGigEPciData(),
pci_bus=0, pci_dev=1, pci_func=0)
etherint = NSGigEInt(device=Parent.ethernet)
console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
class LinuxTsunami(BaseTsunami):
disk0 = LinuxRootDisk(driveID='master')
disk1 = SpecwebFilesetDisk(driveID='slave')
disk2 = LinuxSwapDisk(driveID='master')
ide = IdeController(disks=[Parent.disk0, Parent.disk1, Parent.disk2],
configdata=IdeControllerPciData(),
ide = IdeController(disks=[Parent.disk0, Parent.disk2],
pci_func=0, pci_dev=0, pci_bus=0)
class MyLinuxAlphaSystem(LinuxAlphaSystem):
magicbus = Bus(bus_id=0)
magicbus2 = Bus(bus_id=1)
iobus = Bus(bus_id=0)
membus = Bus(bus_id=1)
bridge = Bridge()
physmem = PhysicalMemory(range = AddrRange('128MB'))
bridge.side_a = magicbus.port
bridge.side_b = magicbus2.port
physmem.port = magicbus2.port
tsunami = LinuxTsunami()
tsunami.cchip.pio = magicbus.port
tsunami.pchip.pio = magicbus.port
tsunami.pciconfig.pio = magicbus.default
tsunami.fake_sm_chip.pio = magicbus.port
tsunami.ethernet.pio = magicbus.port
tsunami.ethernet.dma = magicbus.port
tsunami.ethernet.config = magicbus.port
tsunami.fake_uart1.pio = magicbus.port
tsunami.fake_uart2.pio = magicbus.port
tsunami.fake_uart3.pio = magicbus.port
tsunami.fake_uart4.pio = magicbus.port
tsunami.ide.pio = magicbus.port
tsunami.ide.dma = magicbus.port
tsunami.ide.config = magicbus.port
tsunami.fake_ppc.pio = magicbus.port
tsunami.fake_OROM.pio = magicbus.port
tsunami.fake_pnp_addr.pio = magicbus.port
tsunami.fake_pnp_write.pio = magicbus.port
tsunami.fake_pnp_read0.pio = magicbus.port
tsunami.fake_pnp_read1.pio = magicbus.port
tsunami.fake_pnp_read2.pio = magicbus.port
tsunami.fake_pnp_read3.pio = magicbus.port
tsunami.fake_pnp_read4.pio = magicbus.port
tsunami.fake_pnp_read5.pio = magicbus.port
tsunami.fake_pnp_read6.pio = magicbus.port
tsunami.fake_pnp_read7.pio = magicbus.port
tsunami.fake_ata0.pio = magicbus.port
tsunami.fake_ata1.pio = magicbus.port
tsunami.fb.pio = magicbus.port
tsunami.io.pio = magicbus.port
tsunami.uart.pio = magicbus.port
tsunami.console.pio = magicbus.port
raw_image = RawDiskImage(image_file=disk('linux-latest.img'),
read_only=True)
simple_disk = SimpleDisk(disk=Parent.raw_image)
bridge.side_a = iobus.port
bridge.side_b = membus.port
physmem.port = membus.port
disk0 = CowIdeDisk(driveID='master')
disk2 = CowIdeDisk(driveID='master')
disk0.childImage(linux_image)
disk2.childImage(disk('linux-bigswap2.img'))
tsunami = BaseTsunami()
tsunami.attachIO(iobus)
tsunami.ide.pio = iobus.port
tsunami.ide.dma = iobus.port
tsunami.ide.config = iobus.port
tsunami.ethernet.pio = iobus.port
tsunami.ethernet.dma = iobus.port
tsunami.ethernet.config = iobus.port
simple_disk = SimpleDisk(disk=RawDiskImage(image_file = linux_image,
read_only = True))
intrctrl = IntrControl()
if options.timing:
if options.detailed:
cpu = DetailedO3CPU()
elif options.timing:
cpu = TimingSimpleCPU()
else:
cpu = AtomicSimpleCPU()
cpu.mem = magicbus2
cpu.icache_port = magicbus2.port
cpu.dcache_port = magicbus2.port
cpu.mem = membus
cpu.icache_port = membus.port
cpu.dcache_port = membus.port
cpu.itb = AlphaITB()
cpu.dtb = AlphaDTB()
sim_console = SimConsole(listener=ConsoleListener(port=3456))
@@ -199,14 +77,10 @@ class MyLinuxAlphaSystem(LinuxAlphaSystem):
pal = binary('ts_osfpal')
console = binary('console')
boot_osflags = 'root=/dev/hda1 console=ttyS0'
# readfile = os.path.join(test_base, 'halt.sh')
class TsunamiRoot(System):
class TsunamiRoot(Root):
pass
def DualRoot(clientSystem, serverSystem):
self = Root()
self.client = clientSystem
@@ -219,12 +93,18 @@ def DualRoot(clientSystem, serverSystem):
self.clock = '5GHz'
return self
root = DualRoot(
MyLinuxAlphaSystem(readfile=script('netperf-stream-nt-client.rcS')),
MyLinuxAlphaSystem(readfile=script('netperf-server.rcS')))
if options.dual:
root = DualRoot(
MyLinuxAlphaSystem(readfile=script('netperf-stream-nt-client.rcS')),
MyLinuxAlphaSystem(readfile=script('netperf-server.rcS')))
else:
root = TsunamiRoot(clock = '2GHz', system = MyLinuxAlphaSystem())
m5.instantiate(root)
exit_event = m5.simulate()
if options.maxtick:
exit_event = m5.simulate(options.maxtick)
else:
exit_event = m5.simulate()
print 'Exiting @ cycle', m5.curTick(), 'because', exit_event.getCause()

54
configs/test/test.py
View File

@@ -1,38 +1,13 @@
# Simple test script
#
# Alpha: "m5 test.py"
# MIPS: "m5 test.py -a Mips -c hello_mips"
import os, optparse, sys
# MIPS: "m5 test.py -c hello_mips"
import m5
from m5.objects import *
from FullO3Config import *
import os, optparse, sys
m5.AddToPath('../common')
from SEConfig import *
# parse command-line arguments
parser = optparse.OptionParser()
parser.add_option("-c", "--cmd", default="hello",
help="The binary to run in syscall emulation mode.")
parser.add_option("-o", "--options", default="",
help="The options to pass to the binary, use \" \" around the entire\
string.")
parser.add_option("-i", "--input", default="",
help="A file of input to give to the binary.")
parser.add_option("-t", "--timing", action="store_true",
help="Use simple timing CPU.")
parser.add_option("-d", "--detailed", action="store_true",
help="Use detailed CPU.")
parser.add_option("-m", "--maxtick", type="int",
help="Set the maximum number of ticks to run for")
(options, args) = parser.parse_args()
if args:
print "Error: script doesn't take any positional arguments"
sys.exit(1)
# build configuration
this_dir = os.path.dirname(__file__)
process = LiveProcess()
@@ -41,16 +16,7 @@ process.cmd = options.cmd + " " + options.options
if options.input != "":
process.input = options.input
magicbus = Bus()
mem = PhysicalMemory()
if options.timing and options.detailed:
print "Error: you may only specify one cpu model";
sys.exit(1)
if options.timing:
cpu = TimingSimpleCPU()
elif options.detailed:
if options.detailed:
#check for SMT workload
workloads = options.cmd.split(';')
if len(workloads) > 1:
@@ -70,17 +36,7 @@ elif options.detailed:
process += [smt_process, ]
smt_idx += 1
cpu = DetailedO3CPU()
else:
cpu = AtomicSimpleCPU()
cpu.workload = process
cpu.mem = magicbus
cpu.icache_port=magicbus.port
cpu.dcache_port=magicbus.port
system = System(physmem = mem, cpu = cpu)
mem.port = magicbus.port
root = Root(system = system)
# instantiate configuration
m5.instantiate(root)

2
src/SConscript
View File

@@ -298,7 +298,7 @@ alpha_eio_sources = Split('''
encumbered/eio/eio.cc
''')
if env['TARGET_ISA'] == 'ALPHA_ISA':
if env['TARGET_ISA'] == 'alpha':
syscall_emulation_sources += alpha_eio_sources
memtest_sources = Split('''

12
src/cpu/o3/commit_impl.hh
View File

@@ -996,6 +996,12 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
// Check if the instruction caused a fault. If so, trap.
Fault inst_fault = head_inst->getFault();
// DTB will sometimes need the machine instruction for when
// faults happen. So we will set it here, prior to the DTB
// possibly needing it for its fault.
thread[tid]->setInst(
static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
if (inst_fault != NoFault) {
head_inst->setCompleted();
DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
@@ -1018,12 +1024,6 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
// execution doesn't generate extra squashes.
thread[tid]->inSyscall = true;
// DTB will sometimes need the machine instruction for when
// faults happen. So we will set it here, prior to the DTB
// possibly needing it for its fault.
thread[tid]->setInst(
static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
// Execute the trap. Although it's slightly unrealistic in
// terms of timing (as it doesn't wait for the full timing of
// the trap event to complete before updating state), it's

15
src/cpu/o3/cpu.cc
View File

@@ -765,7 +765,8 @@ template <class Impl>
void
FullO3CPU<Impl>::serialize(std::ostream &os)
{
SERIALIZE_ENUM(_status);
SimObject::State so_state = SimObject::getState();
SERIALIZE_ENUM(so_state);
BaseCPU::serialize(os);
nameOut(os, csprintf("%s.tickEvent", name()));
tickEvent.serialize(os);
@@ -786,7 +787,8 @@ template <class Impl>
void
FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_ENUM(_status);
SimObject::State so_state;
UNSERIALIZE_ENUM(so_state);
BaseCPU::unserialize(cp, section);
tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
@@ -1063,7 +1065,8 @@ template <class Impl>
void
FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
{
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
int idx = reg_idx + TheISA::FP_Base_DepTag;
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
regFile.setFloatReg(phys_reg, val);
}
@@ -1072,7 +1075,8 @@ template <class Impl>
void
FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
{
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
int idx = reg_idx + TheISA::FP_Base_DepTag;
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
regFile.setFloatReg(phys_reg, val, 64);
}
@@ -1081,7 +1085,8 @@ template <class Impl>
void
FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
{
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
int idx = reg_idx + TheISA::FP_Base_DepTag;
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
regFile.setFloatRegBits(phys_reg, val);
}

19
src/cpu/simple/atomic.cc
View File

@@ -158,18 +158,29 @@ AtomicSimpleCPU::~AtomicSimpleCPU()
void
AtomicSimpleCPU::serialize(ostream &os)
{
SERIALIZE_ENUM(_status);
BaseSimpleCPU::serialize(os);
SimObject::State so_state = SimObject::getState();
SERIALIZE_ENUM(so_state);
nameOut(os, csprintf("%s.tickEvent", name()));
tickEvent.serialize(os);
BaseSimpleCPU::serialize(os);
}
void
AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
{
UNSERIALIZE_ENUM(_status);
BaseSimpleCPU::unserialize(cp, section);
SimObject::State so_state;
UNSERIALIZE_ENUM(so_state);
tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
BaseSimpleCPU::unserialize(cp, section);
}
void
AtomicSimpleCPU::resume()
{
if (thread->status() == ThreadContext::Active) {
if (!tickEvent.scheduled())
tickEvent.schedule(curTick);
}
}
void

1
src/cpu/simple/atomic.hh
View File

@@ -126,6 +126,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
virtual void resume();
void switchOut();
void takeOverFrom(BaseCPU *oldCPU);

8
src/cpu/simple/base.cc
View File

@@ -178,8 +178,8 @@ void
BaseSimpleCPU::serialize(ostream &os)
{
BaseCPU::serialize(os);
SERIALIZE_SCALAR(inst);
nameOut(os, csprintf("%s.xc", name()));
// SERIALIZE_SCALAR(inst);
nameOut(os, csprintf("%s.xc.0", name()));
thread->serialize(os);
}
@@ -187,8 +187,8 @@ void
BaseSimpleCPU::unserialize(Checkpoint *cp, const string &section)
{
BaseCPU::unserialize(cp, section);
UNSERIALIZE_SCALAR(inst);
thread->unserialize(cp, csprintf("%s.xc", section));
// UNSERIALIZE_SCALAR(inst);
thread->unserialize(cp, csprintf("%s.xc.0", section));
}
void

10
src/cpu/simple/timing.cc
View File

@@ -102,14 +102,16 @@ TimingSimpleCPU::~TimingSimpleCPU()
void
TimingSimpleCPU::serialize(ostream &os)
{
SERIALIZE_ENUM(_status);
SimObject::State so_state = SimObject::getState();
SERIALIZE_ENUM(so_state);
BaseSimpleCPU::serialize(os);
}
void
TimingSimpleCPU::unserialize(Checkpoint *cp, const string &section)
{
UNSERIALIZE_ENUM(_status);
SimObject::State so_state;
UNSERIALIZE_ENUM(so_state);
BaseSimpleCPU::unserialize(cp, section);
}
@@ -134,7 +136,9 @@ TimingSimpleCPU::resume()
if (_status != SwitchedOut && _status != Idle) {
// Delete the old event if it existed.
if (fetchEvent) {
assert(!fetchEvent->scheduled());
if (fetchEvent->scheduled())
fetchEvent->deschedule();
delete fetchEvent;
}

1
src/cpu/simple_thread.cc
View File

@@ -196,6 +196,7 @@ SimpleThread::copyState(ThreadContext *oldContext)
#if !FULL_SYSTEM
funcExeInst = oldContext->readFuncExeInst();
#endif
inst = oldContext->getInst();
}
void

4
src/python/m5/objects/DiskImage.py
View File

@@ -10,6 +10,6 @@ class RawDiskImage(DiskImage):
class CowDiskImage(DiskImage):
type = 'CowDiskImage'
child = Param.DiskImage("child image")
child = Param.DiskImage(RawDiskImage(read_only=True),
"child image")
table_size = Param.Int(65536, "initial table size")
image_file = ''

45
src/python/m5/objects/Ethernet.py
View File

@@ -1,7 +1,7 @@
from m5 import build_env
from m5.config import *
from Device import DmaDevice
from Pci import PciDevice
from Pci import PciDevice, PciConfigData
class EtherInt(SimObject):
type = 'EtherInt'
@@ -84,6 +84,26 @@ class EtherDevBase(PciDevice):
tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
rss = Param.Bool(False, "Receive Side Scaling")
class NSGigEPciData(PciConfigData):
VendorID = 0x100B
DeviceID = 0x0022
Status = 0x0290
SubClassCode = 0x00
ClassCode = 0x02
ProgIF = 0x00
BAR0 = 0x00000001
BAR1 = 0x00000000
BAR2 = 0x00000000
BAR3 = 0x00000000
BAR4 = 0x00000000
BAR5 = 0x00000000
MaximumLatency = 0x34
MinimumGrant = 0xb0
InterruptLine = 0x1e
InterruptPin = 0x01
BAR0Size = '256B'
BAR1Size = '4kB'
class NSGigE(EtherDevBase):
type = 'NSGigE'
@@ -91,11 +111,32 @@ class NSGigE(EtherDevBase):
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
configdata = NSGigEPciData()
class NSGigEInt(EtherInt):
type = 'NSGigEInt'
device = Param.NSGigE("Ethernet device of this interface")
class SinicPciData(PciConfigData):
VendorID = 0x1291
DeviceID = 0x1293
Status = 0x0290
SubClassCode = 0x00
ClassCode = 0x02
ProgIF = 0x00
BAR0 = 0x00000000
BAR1 = 0x00000000
BAR2 = 0x00000000
BAR3 = 0x00000000
BAR4 = 0x00000000
BAR5 = 0x00000000
MaximumLatency = 0x34
MinimumGrant = 0xb0
InterruptLine = 0x1e
InterruptPin = 0x01
BAR0Size = '64kB'
class Sinic(EtherDevBase):
type = 'Sinic'
@@ -111,6 +152,8 @@ class Sinic(EtherDevBase):
delay_copy = Param.Bool(False, "Delayed copy transmit")
virtual_addr = Param.Bool(False, "Virtual addressing")
configdata = SinicPciData()
class SinicInt(EtherInt):
type = 'SinicInt'
device = Param.Sinic("Ethernet device of this interface")

27
src/python/m5/objects/Ide.py
View File

@@ -1,8 +1,31 @@
from m5.config import *
from Pci import PciDevice
from Pci import PciDevice, PciConfigData
class IdeID(Enum): vals = ['master', 'slave']
class IdeControllerPciData(PciConfigData):
VendorID = 0x8086
DeviceID = 0x7111
Command = 0x0
Status = 0x280
Revision = 0x0
ClassCode = 0x01
SubClassCode = 0x01
ProgIF = 0x85
BAR0 = 0x00000001
BAR1 = 0x00000001
BAR2 = 0x00000001
BAR3 = 0x00000001
BAR4 = 0x00000001
BAR5 = 0x00000001
InterruptLine = 0x1f
InterruptPin = 0x01
BAR0Size = '8B'
BAR1Size = '4B'
BAR2Size = '8B'
BAR3Size = '4B'
BAR4Size = '16B'
class IdeDisk(SimObject):
type = 'IdeDisk'
delay = Param.Latency('1us', "Fixed disk delay in microseconds")
@@ -12,3 +35,5 @@ class IdeDisk(SimObject):
class IdeController(PciDevice):
type = 'IdeController'
disks = VectorParam.IdeDisk("IDE disks attached to this controller")
configdata =IdeControllerPciData()

77
src/python/m5/objects/Tsunami.py
View File

@@ -1,11 +1,10 @@
from m5.config import *
from Device import BasicPioDevice
from Platform import Platform
class Tsunami(Platform):
type = 'Tsunami'
# pciconfig = Param.PciConfigAll("PCI configuration")
system = Param.System(Parent.any, "system")
from AlphaConsole import AlphaConsole
from Uart import Uart8250
from Pci import PciConfigAll
from BadDevice import BadDevice
class TsunamiCChip(BasicPioDevice):
type = 'TsunamiCChip'
@@ -25,3 +24,71 @@ class TsunamiIO(BasicPioDevice):
class TsunamiPChip(BasicPioDevice):
type = 'TsunamiPChip'
tsunami = Param.Tsunami(Parent.any, "Tsunami")
class Tsunami(Platform):
type = 'Tsunami'
system = Param.System(Parent.any, "system")
cchip = TsunamiCChip(pio_addr=0x801a0000000)
pchip = TsunamiPChip(pio_addr=0x80180000000)
pciconfig = PciConfigAll()
fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
fake_ppc = IsaFake(pio_addr=0x801fc0003bc)
fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
fake_ata1 = IsaFake(pio_addr=0x801fc000170)
fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
io = TsunamiIO(pio_addr=0x801fc000000)
uart = Uart8250(pio_addr=0x801fc0003f8)
console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
self.cchip.pio = bus.port
self.pchip.pio = bus.port
self.pciconfig.pio = bus.default
self.fake_sm_chip.pio = bus.port
self.fake_uart1.pio = bus.port
self.fake_uart2.pio = bus.port
self.fake_uart3.pio = bus.port
self.fake_uart4.pio = bus.port
self.fake_ppc.pio = bus.port
self.fake_OROM.pio = bus.port
self.fake_pnp_addr.pio = bus.port
self.fake_pnp_write.pio = bus.port
self.fake_pnp_read0.pio = bus.port
self.fake_pnp_read1.pio = bus.port
self.fake_pnp_read2.pio = bus.port
self.fake_pnp_read3.pio = bus.port
self.fake_pnp_read4.pio = bus.port
self.fake_pnp_read5.pio = bus.port
self.fake_pnp_read6.pio = bus.port
self.fake_pnp_read7.pio = bus.port
self.fake_ata0.pio = bus.port
self.fake_ata1.pio = bus.port
self.fb.pio = bus.port
self.io.pio = bus.port
self.uart.pio = bus.port
self.console.pio = bus.port