arch-x86: Create a separate type for floating point reg idxs.

This will ensure that floating point registers are used when required
and never otherwise.

Change-Id: I303c42d8a74c56b7b433b91fd36dc6aaf5ddef32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42354
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/x86/insts/microldstop.hh

@@ -101,7 +101,7 @@ class LdStFpOp : public InstOperands<MemOp, FloatDataOp, AddrOp>
 {
   protected:
     LdStFpOp(ExtMachInst mach_inst, const char *mnem, const char *inst_mnem,
-            uint64_t set_flags, InstRegIndex _data,
+            uint64_t set_flags, FpRegIndex _data,
             uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
             uint64_t _disp, InstRegIndex _segment,
             uint8_t data_size, uint8_t address_size,

src/arch/x86/insts/microop_args.hh

@@ -194,10 +194,10 @@ struct MiscOp : public Base
 template <class Base>
 struct FloatOp : public Base
 {
+    using ArgType = FpRegIndex;
+
     template <class InstType>
-    FloatOp(InstType *inst, typename Base::ArgType idx) :
-        Base(idx.index, inst->dataSize)
-    {}
+    FloatOp(InstType *inst, ArgType idx) : Base(idx.index, inst->dataSize) {}
 
     void
     print(std::ostream &os) const

src/arch/x86/insts/static_inst.hh

@@ -46,7 +46,7 @@ namespace X86ISA
 {
 
 /**
- * Class for register indices passed to instruction constructors. Using a
+ * Classes for register indices passed to instruction constructors. Using a
  * wrapper struct for these lets take advantage of the compiler's type
  * checking.
  */
@@ -56,6 +56,12 @@ struct InstRegIndex
     explicit InstRegIndex(RegIndex idx) : index(idx) {}
 };
 
+struct FpRegIndex
+{
+    RegIndex index;
+    explicit FpRegIndex(RegIndex idx) : index(idx) {}
+};
+
 /**
  * Base class for all X86 static instructions.
  */

src/arch/x86/isa/includes.isa

@@ -70,6 +70,8 @@ output header {{
 #include "sim/faults.hh"
 
 using X86ISA::InstRegIndex;
+using X86ISA::FpRegIndex;
+
 }};
 
 output decoder {{

src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py

@@ -43,16 +43,16 @@ storeX87RegTemplate = '''
 '''
 
 loadXMMRegTemplate =  '''
-    ldfp regIdx("FLOATREG_XMM_LOW(%(idx)i)"), seg, %(mode)s, \
+    ldfp fpRegIdx("FLOATREG_XMM_LOW(%(idx)i)"), seg, %(mode)s, \
          "DISPLACEMENT + 160 + 16 * %(idx)i", dataSize=8
-    ldfp regIdx("FLOATREG_XMM_HIGH(%(idx)i)"), seg, %(mode)s, \
+    ldfp fpRegIdx("FLOATREG_XMM_HIGH(%(idx)i)"), seg, %(mode)s, \
          "DISPLACEMENT + 160 + 16 * %(idx)i + 8", dataSize=8
 '''
 
 storeXMMRegTemplate =  '''
-    stfp regIdx("FLOATREG_XMM_LOW(%(idx)i)"), seg, %(mode)s, \
+    stfp fpRegIdx("FLOATREG_XMM_LOW(%(idx)i)"), seg, %(mode)s, \
          "DISPLACEMENT + 160 + 16 * %(idx)i", dataSize=8
-    stfp regIdx("FLOATREG_XMM_HIGH(%(idx)i)"), seg, %(mode)s, \
+    stfp fpRegIdx("FLOATREG_XMM_HIGH(%(idx)i)"), seg, %(mode)s, \
          "DISPLACEMENT + 160 + 16 * %(idx)i + 8", dataSize=8
 '''
 

src/arch/x86/isa/microasm.isa

@@ -57,16 +57,19 @@ let {{
     assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop)
 
     def regIdx(idx):
-        return "InstRegIndex(%s)" % idx
+        return "X86ISA::InstRegIndex(%s)" % idx
+    def fpRegIdx(idx):
+        return "X86ISA::FpRegIndex(%s)" % idx
 
     assembler.symbols["regIdx"] = regIdx
+    assembler.symbols["fpRegIdx"] = fpRegIdx
 
     # Add in symbols for the microcode registers
     for num in range(16):
         assembler.symbols["t%d" % num] = regIdx("NUM_INTREGS+%d" % num)
     for num in range(8):
         assembler.symbols["ufp%d" % num] = \
-            regIdx("FLOATREG_MICROFP(%d)" % num)
+            fpRegIdx("FLOATREG_MICROFP(%d)" % num)
     # Add in symbols for the segment descriptor registers
     for letter in ("C", "D", "E", "F", "G", "H", "S"):
         assembler.symbols["%ss" % letter.lower()] = \
@@ -87,13 +90,13 @@ let {{
     # Miscellaneous symbols
     symbols = {
         "reg" : regIdx("env.reg"),
-        "xmml" : regIdx("FLOATREG_XMM_LOW(env.reg)"),
-        "xmmh" : regIdx("FLOATREG_XMM_HIGH(env.reg)"),
+        "xmml" : fpRegIdx("FLOATREG_XMM_LOW(env.reg)"),
+        "xmmh" : fpRegIdx("FLOATREG_XMM_HIGH(env.reg)"),
         "regm" : regIdx("env.regm"),
-        "xmmlm" : regIdx("FLOATREG_XMM_LOW(env.regm)"),
-        "xmmhm" : regIdx("FLOATREG_XMM_HIGH(env.regm)"),
-        "mmx" : regIdx("FLOATREG_MMX(env.reg)"),
-        "mmxm" : regIdx("FLOATREG_MMX(env.regm)"),
+        "xmmlm" : fpRegIdx("FLOATREG_XMM_LOW(env.regm)"),
+        "xmmhm" : fpRegIdx("FLOATREG_XMM_HIGH(env.regm)"),
+        "mmx" : fpRegIdx("FLOATREG_MMX(env.reg)"),
+        "mmxm" : fpRegIdx("FLOATREG_MMX(env.regm)"),
         "imm" : "adjustedImm",
         "disp" : "adjustedDisp",
         "seg" : regIdx("env.seg"),
@@ -205,7 +208,7 @@ let {{
     assembler.symbols["rom_local_label"] = rom_local_labeler
 
     def stack_index(index):
-        return regIdx("NUM_FLOATREGS + (((%s) + 8) %% 8)" % index)
+        return fpRegIdx("NUM_FLOATREGS + (((%s) + 8) %% 8)" % index)
 
     assembler.symbols["st"] = stack_index
     assembler.symbols["sti"] = stack_index("env.reg")