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add in an init() callback for CPU's so that no stats are accessed prior to the end of the build process. (Done by doing the registerExecContext() calling sequence in the init() process rather than the create() process).

Browse Source 
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
    same thing for simple cpu's.

--HG--
extra : convert_revision : aac9f91742866fb26f8cace622f9b88454a69662
This commit is contained in:
Lisa Hsu
2004-02-24 14:59:25 -05:00
parent f9c91277f3
commit 6a306d4caf
2 changed files with 23 additions and 8 deletions
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23
cpu/simple_cpu/simple_cpu.cc
View File

@@ -120,7 +120,7 @@ SimpleCPU::SimpleCPU(const string &_name,
FunctionalMemory *mem,
MemInterface *icache_interface,
MemInterface *dcache_interface,
Tick freq)
bool _def_reg, Tick freq)
: BaseCPU(_name, /* number_of_threads */ 1,
max_insts_any_thread, max_insts_all_threads,
max_loads_any_thread, max_loads_all_threads,
@@ -132,12 +132,14 @@ SimpleCPU::SimpleCPU(const string &_name, Process *_process,
Counter max_loads_any_thread,
Counter max_loads_all_threads,
MemInterface *icache_interface,
MemInterface *dcache_interface)
MemInterface *dcache_interface,
bool _def_reg)
: BaseCPU(_name, /* number_of_threads */ 1,
max_insts_any_thread, max_insts_all_threads,
max_loads_any_thread, max_loads_all_threads),
#endif
tickEvent(this), xc(NULL), cacheCompletionEvent(this)
tickEvent(this), xc(NULL), defer_registration(_def_reg),
cacheCompletionEvent(this)
{
_status = Idle;
#ifdef FULL_SYSTEM
@@ -171,6 +173,13 @@ SimpleCPU::~SimpleCPU()
{
}
void SimpleCPU::init()
{
if (!defer_registration) {
this->registerExecContexts();
}
}
void
SimpleCPU::switchOut()
{
@@ -810,6 +819,7 @@ CREATE_SIM_OBJECT(SimpleCPU)
itb, dtb, mem,
(icache) ? icache->getInterface() : NULL,
(dcache) ? dcache->getInterface() : NULL,
defer_registration,
ticksPerSecond * mult);
#else
@@ -817,14 +827,15 @@ CREATE_SIM_OBJECT(SimpleCPU)
max_insts_any_thread, max_insts_all_threads,
max_loads_any_thread, max_loads_all_threads,
(icache) ? icache->getInterface() : NULL,
(dcache) ? dcache->getInterface() : NULL);
(dcache) ? dcache->getInterface() : NULL,
defer_registration);
#endif // FULL_SYSTEM
#if 0
if (!defer_registration) {
cpu->registerExecContexts();
}
#endif
return cpu;
}

8
cpu/simple_cpu/simple_cpu.hh
View File

@@ -133,7 +133,7 @@ class SimpleCPU : public BaseCPU
Counter max_loads_any_thread, Counter max_loads_all_threads,
AlphaItb *itb, AlphaDtb *dtb, FunctionalMemory *mem,
MemInterface *icache_interface, MemInterface *dcache_interface,
Tick freq);
bool _def_reg, Tick freq);
#else
@@ -142,11 +142,13 @@ class SimpleCPU : public BaseCPU
Counter max_insts_all_threads,
Counter max_loads_any_thread,
Counter max_loads_all_threads,
MemInterface *icache_interface, MemInterface *dcache_interface);
MemInterface *icache_interface, MemInterface *dcache_interface,
bool _def_reg);
#endif
virtual ~SimpleCPU();
virtual void init();
// execution context
ExecContext *xc;
@@ -166,6 +168,8 @@ class SimpleCPU : public BaseCPU
// L1 data cache
MemInterface *dcacheInterface;
bool defer_registration;
// current instruction
MachInst inst;