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moved ev5_trap fully into the fault class.

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--HG--
extra : convert_revision : 182cdec9a4e05f55edff0c6a114844b9ad2ca8db
This commit is contained in:
Gabe Black
2006-03-01 00:09:08 -05:00
parent 34da58a698
commit 69e91d7617
4 changed files with 30 additions and 51 deletions
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32
arch/alpha/ev5.cc
View File

@@ -163,38 +163,6 @@ AlphaISA::zeroRegisters(CPU *cpu)
cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
}
void
ExecContext::ev5_temp_trap(Fault fault)
{
DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name(), regs.pc);
cpu->recordEvent(csprintf("Fault %s", fault->name()));
assert(!misspeculating());
kernelStats->fault(fault);
if (fault->isA<ArithmeticFault>())
panic("Arithmetic traps are unimplemented!");
// exception restart address
if (!fault->isA<InterruptFault>() || !inPalMode())
setMiscReg(AlphaISA::IPR_EXC_ADDR, regs.pc);
if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* ||
fault == InterruptFault && !inPalMode() */) {
// traps... skip faulting instruction.
setMiscReg(AlphaISA::IPR_EXC_ADDR,
readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
}
if (!inPalMode())
AlphaISA::swap_palshadow(&regs, true);
regs.pc = readMiscReg(AlphaISA::IPR_PAL_BASE) +
(dynamic_cast<AlphaFault *>(fault.get()))->vect();
regs.npc = regs.pc + sizeof(MachInst);
}
void
AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
{

34
arch/alpha/faults.cc
View File

@@ -28,6 +28,9 @@
#include "arch/alpha/faults.hh"
#include "cpu/exec_context.hh"
#include "cpu/base.hh"
#include "base/trace.hh"
#include "kern/kernel_stats.hh"
namespace AlphaISA
{
@@ -98,17 +101,30 @@ FaultStat IntegerOverflowFault::_stat;
void AlphaFault::ev5_trap(ExecContext * xc)
{
xc->ev5_temp_trap(this);
}
DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->regs.pc);
xc->cpu->recordEvent(csprintf("Fault %s", name()));
void AlphaMachineCheckFault::ev5_trap(ExecContext * xc)
{
xc->ev5_temp_trap(this);
}
assert(!xc->misspeculating());
xc->kernelStats->fault(this);
void AlphaAlignmentFault::ev5_trap(ExecContext * xc)
{
xc->ev5_temp_trap(this);
if (isA<ArithmeticFault>())
panic("Arithmetic traps are unimplemented!");
// exception restart address
if (!isA<InterruptFault>() || !xc->inPalMode())
xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc);
if (isA<PalFault>() || isA<ArithmeticFault>()) {
// traps... skip faulting instruction.
xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
}
if (!xc->inPalMode())
AlphaISA::swap_palshadow(&(xc->regs), true);
xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
xc->regs.npc = xc->regs.pc + sizeof(MachInst);
}
#endif

6
arch/alpha/faults.hh
View File

@@ -55,9 +55,6 @@ class AlphaMachineCheckFault :
static FaultVect _vect;
static FaultStat _stat;
public:
#if FULL_SYSTEM
void ev5_trap(ExecContext * xc);
#endif
FaultVect vect() {return _vect;}
FaultStat & stat() {return _stat;}
};
@@ -70,9 +67,6 @@ class AlphaAlignmentFault :
static FaultVect _vect;
static FaultStat _stat;
public:
#if FULL_SYSTEM
void ev5_trap(ExecContext * xc);
#endif
FaultVect vect() {return _vect;}
FaultStat & stat() {return _stat;}
};

9
cpu/o3/alpha_cpu_impl.hh
View File

@@ -302,7 +302,7 @@ template <class Impl>
void
AlphaFullCPU<Impl>::trap(Fault fault)
{
// Keep in mind that a trap may be initiated by fetch if there's a TLB
/* // Keep in mind that a trap may be initiated by fetch if there's a TLB
// miss
uint64_t PC = this->commit.readCommitPC();
@@ -318,8 +318,9 @@ AlphaFullCPU<Impl>::trap(Fault fault)
if (!fault->isA<InterruptFault>() || !inPalMode(PC))
this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR, PC);
if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* ||
fault == InterruptFault && !PC_PAL(regs.pc) */) {
if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>())
// || fault == InterruptFault && !PC_PAL(regs.pc)
{
// traps... skip faulting instruction
AlphaISA::MiscReg ipr_exc_addr =
this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR);
@@ -332,7 +333,7 @@ AlphaFullCPU<Impl>::trap(Fault fault)
this->regFile.setPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_PAL_BASE) +
(dynamic_cast<AlphaFault *>(fault.get()))->vect());
this->regFile.setNextPC(PC + sizeof(MachInst));
this->regFile.setNextPC(PC + sizeof(MachInst));*/
}
template <class Impl>