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Updated FastCPU model with all the recent changes.

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arch/alpha/ev5.cc:
    Updated to support new forms of setIntReg and setFloatRegDouble.  Will need to be cleaned up in the future.
arch/isa_parser.py:
    Added in FastCPU model.

--HG--
extra : convert_revision : 384a27efcb50729ea6c3cc11653f395c300e48db
This commit is contained in:
Kevin Lim
2004-05-28 14:42:59 -04:00
parent 67b5f6afc1
commit 6964ecd1cf
2 changed files with 7 additions and 2 deletions
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6
arch/alpha/ev5.cc
View File

@@ -153,8 +153,10 @@ void
AlphaISA::zeroRegisters(XC *xc)
{
// Insure ISA semantics
xc->setIntReg(ZeroReg, 0);
xc->setFloatRegDouble(ZeroReg, 0.0);
// (no longer very clean due to the change in setIntReg() in the
// cpu model. Consider changing later.)
xc->xc->setIntReg(ZeroReg, 0);
xc->xc->setFloatRegDouble(ZeroReg, 0.0);
}
void

3
arch/isa_parser.py
View File

@@ -630,6 +630,9 @@ class CpuModel:
CpuModel('SimpleCPU', 'simple_cpu_exec.cc',
'#include "cpu/simple_cpu/simple_cpu.hh"',
{ 'CPU_exec_context': 'SimpleCPU' })
CpuModel('FastCPU', 'fast_cpu_exec.cc',
'#include "cpu/fast_cpu/fast_cpu.hh"',
{ 'CPU_exec_context': 'FastCPU' })
CpuModel('FullCPU', 'full_cpu_exec.cc',
'#include "cpu/full_cpu/dyn_inst.hh"',
{ 'CPU_exec_context': 'DynInst' })