derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-arm: Fix PCAlignmentFault routing to Hypervisor

Browse Source 
This patch enables PCAlignmentFault routing to Hypervisor in case
HCR_EL2.TGE == 1, as is happening for other arm exceptions.

Change-Id: I48364ef1a0bcb5d030135221ae4bc6429e32759e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8841
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2018-02-20 13:33:34 +00:00
parent 208b1fc47e
commit 689221c651
2 changed files with 15 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/arch/arm/faults.cc
View File

@@ -1432,6 +1432,20 @@ PCAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
tc->setMiscReg(getFaultAddrReg64(), faultPC);
}
bool
PCAlignmentFault::routeToHyp(ThreadContext *tc) const
{
bool toHyp = false;
SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0);
return toHyp;
}
SPAlignmentFault::SPAlignmentFault()
{}

1
src/arch/arm/faults.hh
View File

@@ -535,6 +535,7 @@ class PCAlignmentFault : public ArmFaultVals<PCAlignmentFault>
{}
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr) override;
bool routeToHyp(ThreadContext *tc) const override;
};
/// Stack pointer alignment fault (AArch64 only)