Little fixes to make more of the stats reset correctly.

base/statistics.cc:
    formatting
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
    Make numInsts reset by adding a resetStats function
sim/sim_object.cc:
    Register the reset callback in a slightly cleaner way to avoid
    potential static member constructor ordering issues

--HG--
extra : convert_revision : 408073b4b0397fbf9dfd9c548a313f1c8c3fc031
This commit is contained in:
Nathan Binkert
2003-11-06 00:41:14 -05:00
parent 22658f2098
commit 655e9ef3de
4 changed files with 39 additions and 26 deletions

View File

@@ -160,7 +160,6 @@ Database::~Database()
void
Database::dump(ostream &stream)
{
#ifndef FS_MEASURE
list_t::iterator i = printStats.begin();
list_t::iterator end = printStats.end();
@@ -179,7 +178,7 @@ Database::dump(ostream &stream)
ccprintf(stream, "PRINTING BINNED STATS\n");
while (j != bins_end) {
(*j)->activate();
map<const GenBin *, std::string>::const_iterator iter;
map<const GenBin *, std::string>::const_iterator iter;
iter = bin_names.find(*j);
if (iter == bin_names.end())
panic("a binned stat not found in names map!");
@@ -187,19 +186,19 @@ Database::dump(ostream &stream)
#ifdef FS_MEASURE
list_t::iterator i = printStats.begin();
list_t::iterator end = printStats.end();
list_t::iterator end = printStats.end();
#else
list_t::iterator i = binnedStats.begin();
list_t::iterator end = binnedStats.end();
list_t::iterator i = binnedStats.begin();
list_t::iterator end = binnedStats.end();
#endif
while (i != end) {
Stat *stat = *i;
if (stat->dodisplay())
stat->display(stream);
++i;
}
++j;
ccprintf(stream, "---------------------------------\n");
while (i != end) {
Stat *stat = *i;
if (stat->dodisplay())
stat->display(stream);
++i;
}
++j;
ccprintf(stream, "---------------------------------\n");
}
#ifndef FS_MEASURE
ccprintf(stream, "**************ALL STATS************\n");

View File

@@ -159,7 +159,9 @@ SimpleCPU::SimpleCPU(const string &_name, Process *_process,
memReq->data = new uint8_t[64];
numInst = 0;
startNumInst = 0;
numLoad = 0;
startNumLoad = 0;
lastIcacheStall = 0;
lastDcacheStall = 0;
@@ -215,6 +217,8 @@ SimpleCPU::execCtxStatusChg(int thread_num) {
void
SimpleCPU::regStats()
{
using namespace Statistics;
BaseCPU::regStats();
numInsts
@@ -244,10 +248,16 @@ SimpleCPU::regStats()
.prereq(dcacheStallCycles)
;
numInsts = Statistics::scalar(numInst);
numInsts = Statistics::scalar(numInst) - Statistics::scalar(startNumInst);
simInsts += numInsts;
}
void
SimpleCPU::resetStats()
{
startNumInst = numInst;
}
void
SimpleCPU::serialize(ostream &os)
{

View File

@@ -231,10 +231,12 @@ class SimpleCPU : public BaseCPU
}
// statistics
void regStats();
virtual void regStats();
virtual void resetStats();
// number of simulated instructions
Counter numInst;
Counter startNumInst;
Statistics::Formula numInsts;
// number of simulated memory references
@@ -242,6 +244,7 @@ class SimpleCPU : public BaseCPU
// number of simulated loads
Counter numLoad;
Counter startNumLoad;
// number of idle cycles
Statistics::Average<> idleFraction;

View File

@@ -73,16 +73,6 @@ SimObject::regFormulas()
{
}
namespace {
class __SimObjectResetCB : public Callback
{
public:
__SimObjectResetCB() { Statistics::RegResetCallback(this); }
virtual void process() { SimObject::resetAllStats(); }
};
__SimObjectResetCB __theSimObjectResetCB;
}
void
SimObject::resetStats()
{
@@ -101,6 +91,15 @@ SimObject::printExtraOutput(ostream &os)
// call regStats() on all SimObjects and then regFormulas() on all
// SimObjects.
//
struct SimObjectResetCB : public Callback
{
virtual void process() { SimObject::resetAllStats(); }
};
namespace {
static SimObjectResetCB StatResetCB;
}
void
SimObject::regAllStats()
{
@@ -122,7 +121,9 @@ SimObject::regAllStats()
cprintf("registering formulas for %s\n", (*i)->name());
#endif
(*i)->regFormulas();
}
}
Statistics::RegResetCallback(&StatResetCB);
}
//