arch-riscv: Simplify the rev8 and brev8 instructions
These mnemonic of instructions should not have 'rv32_' prefix Change-Id: Ic072ba8b84e5a51be060e5d7ca16dd913c318957 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70599 Reviewed-by: Yu-hsin Wang <yuhsingw@google.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
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@@ -667,44 +667,24 @@ decode QUADRANT default Unknown::unknown() {
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| (Rs1 << ((xlen - imm) & (xlen - 1))));
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}}, imm_type = uint64_t, imm_code = {{ imm = SHAMT6; }});
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0xd: decode RS2 {
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0x18: decode BIT25 {
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0x0: rv32_rev8({{
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uint32_t result = 0;
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result |=
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((Rs1_uw & 0xffUL) << 24)
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| (((Rs1_uw >> 24) & 0xffUL));
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result |=
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(((Rs1_uw >> 8) & 0xffUL) << 16)
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| (((Rs1_uw >> 16) & 0xffUL) << 8);
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Rd = rvSext(result);
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}},
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imm_type = uint64_t, imm_code = {{ imm = SHAMT5; }});
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0x1: rev8({{
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uint64_t result = 0;
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result |=
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((Rs1 & 0xffULL) << 56)
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| (((Rs1 >> 56) & 0xffULL));
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result |=
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(((Rs1 >> 8) & 0xffULL) << 48)
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| (((Rs1 >> 48) & 0xffULL) << 8);
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result |=
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(((Rs1 >> 16) & 0xffULL) << 40)
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| (((Rs1 >> 40) & 0xffULL) << 16);
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result |=
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(((Rs1 >> 24) & 0xffULL) << 32)
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| (((Rs1 >> 32) & 0xffULL) << 24);
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Rd = result;
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}},
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imm_type = uint64_t, imm_code = {{ imm = SHAMT6; }});
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}
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0x07: decode RVTYPE {
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0x0: rv32_brev8({{
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Rd_sw = _rvk_emu_brev8_32(Rs1_sw);
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}}, imm_code = {{ imm = SHAMT5; }});
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0x1: brev8({{
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Rd = _rvk_emu_brev8_64(Rs1);
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}}, imm_code = {{ imm = SHAMT6; }});
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}
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0x18: ROp::rev8({{
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if (rvSelect((bool)SHAMT6BIT5, false)) {
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return std::make_shared<IllegalInstFault>(
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"shmat[5] != 0", machInst);
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}
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if (machInst.rv_type == RV32) {
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Rd_sd = _rvk_emu_grev_32(Rs1_sd, 0x18);
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} else {
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Rd_sd = _rvk_emu_grev_64(Rs1_sd, 0x38);
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}
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}});
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0x07: ROp::brev8({{
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if (machInst.rv_type == RV32) {
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Rd_sd = _rvk_emu_brev8_32(Rs1_sd);
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} else {
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Rd_sd = _rvk_emu_brev8_64(Rs1_sd);
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}
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}});
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}
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}
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0x6: ori({{
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