dev,cpu,configs: Get rid of the IntrControl device.

This vestigial device provides a thin layer of indirection between
devices and the CPUs in a system. It's basically a collection of helper
functions, but since it's a SimObject it needs to be instantiated in
python and added to configurations.

Change-Id: I029d2314ae0bb890678e1e68dafcdab4bfe49beb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43347
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/dev/arm/RealView.py

@@ -649,7 +649,6 @@ class GenericMHU(MHU):
 class RealView(Platform):
     type = 'RealView'
     cxx_header = "dev/arm/realview.hh"
-    system = Param.System(Parent.any, "system")
     _mem_regions = [ AddrRange(0, size='256MiB') ]
     _num_pci_dev = 0
 

src/dev/arm/gic_v2.cc

@@ -41,6 +41,7 @@
 #include "dev/arm/gic_v2.hh"
 
 #include "base/trace.hh"
+#include "cpu/base.hh"
 #include "debug/Checkpoint.hh"
 #include "debug/GIC.hh"
 #include "debug/IPI.hh"
@@ -917,10 +918,11 @@ GicV2::clearPPInt(uint32_t num, uint32_t cpu)
 void
 GicV2::clearInt(ContextID ctx, uint32_t int_num)
 {
+    auto tc = sys->threads[ctx];
     if (isFiq(ctx, int_num)) {
-        platform->intrctrl->clear(ctx, ArmISA::INT_FIQ, 0);
+        tc->getCpuPtr()->clearInterrupt(tc->threadId(), ArmISA::INT_FIQ, 0);
     } else {
-        platform->intrctrl->clear(ctx, ArmISA::INT_IRQ, 0);
+        tc->getCpuPtr()->clearInterrupt(tc->threadId(), ArmISA::INT_IRQ, 0);
     }
 }
 
@@ -936,7 +938,8 @@ GicV2::postInt(uint32_t cpu, Tick when)
 void
 GicV2::postDelayedInt(uint32_t cpu)
 {
-    platform->intrctrl->post(cpu, ArmISA::INT_IRQ, 0);
+    auto tc = sys->threads[cpu];
+    tc->getCpuPtr()->postInterrupt(tc->threadId(), ArmISA::INT_IRQ, 0);
     --pendingDelayedInterrupts;
     assert(pendingDelayedInterrupts >= 0);
     if (pendingDelayedInterrupts == 0)
@@ -961,7 +964,8 @@ GicV2::supportsVersion(GicVersion version)
 void
 GicV2::postDelayedFiq(uint32_t cpu)
 {
-    platform->intrctrl->post(cpu, ArmISA::INT_FIQ, 0);
+    auto tc = sys->threads[cpu];
+    tc->getCpuPtr()->postInterrupt(tc->threadId(), ArmISA::INT_FIQ, 0);
     --pendingDelayedInterrupts;
     assert(pendingDelayedInterrupts >= 0);
     if (pendingDelayedInterrupts == 0)

src/dev/arm/gic_v2.hh

@@ -51,7 +51,6 @@
 #include "arch/arm/interrupts.hh"
 #include "base/addr_range.hh"
 #include "base/bitunion.hh"
-#include "cpu/intr_control.hh"
 #include "dev/arm/base_gic.hh"
 #include "dev/io_device.hh"
 #include "dev/platform.hh"

src/dev/arm/gic_v2m.hh

@@ -45,7 +45,6 @@
 #define __DEV_ARM_GIC_V2M_H__
 
 #include "base/bitunion.hh"
-#include "cpu/intr_control.hh"
 #include "dev/arm/base_gic.hh"
 #include "dev/io_device.hh"
 #include "dev/platform.hh"

src/dev/arm/gic_v3.cc

@@ -40,7 +40,7 @@
 
 #include "dev/arm/gic_v3.hh"
 
-#include "cpu/intr_control.hh"
+#include "cpu/base.hh"
 #include "debug/GIC.hh"
 #include "debug/Interrupt.hh"
 #include "dev/arm/gic_v3_cpu_interface.hh"
@@ -204,8 +204,9 @@ Gicv3::clearPPInt(uint32_t int_id, uint32_t cpu)
 void
 Gicv3::postInt(uint32_t cpu, ArmISA::InterruptTypes int_type)
 {
-    platform->intrctrl->post(cpu, int_type, 0);
-    ArmSystem::callClearStandByWfi(sys->threads[cpu]);
+    auto tc = sys->threads[cpu];
+    tc->getCpuPtr()->postInterrupt(tc->threadId(), int_type, 0);
+    ArmSystem::callClearStandByWfi(tc);
 }
 
 bool
@@ -218,19 +219,22 @@ Gicv3::supportsVersion(GicVersion version)
 void
 Gicv3::deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type)
 {
-    platform->intrctrl->clear(cpu, int_type, 0);
+    auto tc = sys->threads[cpu];
+    tc->getCpuPtr()->clearInterrupt(tc->threadId(), int_type, 0);
 }
 
 void
 Gicv3::deassertAll(uint32_t cpu)
 {
-    platform->intrctrl->clearAll(cpu);
+    auto tc = sys->threads[cpu];
+    tc->getCpuPtr()->clearInterrupts(tc->threadId());
 }
 
 bool
 Gicv3::haveAsserted(uint32_t cpu) const
 {
-    return platform->intrctrl->havePosted(cpu);
+    auto tc = sys->threads[cpu];
+    return tc->getCpuPtr()->checkInterrupts(tc->threadId());
 }
 
 Gicv3Redistributor *

src/dev/arm/realview.cc

@@ -48,13 +48,11 @@
 #include <string>
 #include <vector>
 
-#include "cpu/intr_control.hh"
 #include "dev/arm/base_gic.hh"
-#include "sim/system.hh"
 
 
 RealView::RealView(const Params &p)
-    : Platform(p), system(p.system), gic(nullptr)
+    : Platform(p), gic(nullptr)
 {}
 
 void

src/dev/arm/realview.hh

@@ -52,25 +52,15 @@
 
 class BaseGic;
 class IdeController;
-class System;
 
 class RealView : public Platform
 {
   public:
-    /** Pointer to the system */
-    System *system;
-
     BaseGic *gic;
 
   public:
     using Params = RealViewParams;
 
-    /**
-     * Constructor for the Tsunami Class.
-     * @param name name of the object
-     * @param s system the object belongs to
-     * @param intctrl pointer to the interrupt controller
-     */
     RealView(const Params &p);
 
     /** Give platform a pointer to interrupt controller */

src/dev/arm/vgic.cc

@@ -39,6 +39,7 @@
 
 #include "arch/arm/interrupts.hh"
 #include "base/trace.hh"
+#include "cpu/base.hh"
 #include "debug/Checkpoint.hh"
 #include "debug/VGIC.hh"
 #include "dev/arm/base_gic.hh"
@@ -371,13 +372,15 @@ void
 VGic::unPostVInt(uint32_t cpu)
 {
     DPRINTF(VGIC, "Unposting VIRQ to %d\n", cpu);
-    platform->intrctrl->clear(cpu, ArmISA::INT_VIRT_IRQ, 0);
+    auto tc = platform->system->threads[cpu];
+    tc->getCpuPtr()->clearInterrupt(tc->threadId(), ArmISA::INT_VIRT_IRQ, 0);
 }
 
 void
 VGic::processPostVIntEvent(uint32_t cpu)
 {
-     platform->intrctrl->post(cpu, ArmISA::INT_VIRT_IRQ, 0);
+    auto tc = platform->system->threads[cpu];
+    tc->getCpuPtr()->postInterrupt(tc->threadId(), ArmISA::INT_VIRT_IRQ, 0);
 }
 
 

src/dev/arm/vgic.hh

@@ -55,7 +55,6 @@
 
 #include "base/addr_range.hh"
 #include "base/bitunion.hh"
-#include "cpu/intr_control.hh"
 #include "dev/io_device.hh"
 #include "dev/platform.hh"
 #include "params/VGic.hh"