dev,cpu,configs: Get rid of the IntrControl device.

This vestigial device provides a thin layer of indirection between
devices and the CPUs in a system. It's basically a collection of helper
functions, but since it's a SimObject it needs to be instantiated in
python and added to configurations.

Change-Id: I029d2314ae0bb890678e1e68dafcdab4bfe49beb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43347
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/cpu/SConscript

@@ -64,7 +64,6 @@ DebugFlag('ExecAsid', 'Format: Include ASID in trace')
 DebugFlag('ExecFlags', 'Format: Include instruction flags in trace')
 DebugFlag('Fetch')
 DebugFlag('HtmCpu', 'Hardware Transactional Memory (CPU side)')
-DebugFlag('IntrControl')
 DebugFlag('O3PipeView')
 DebugFlag('PCEvent')
 DebugFlag('Quiesce')
@@ -83,8 +82,6 @@ CompoundFlag('ExecNoTicks', [ 'Exec', 'FmtTicksOff' ])
 Source('pc_event.cc')
 
 if env['TARGET_ISA'] == 'null':
-    SimObject('IntrControl.py')
-    Source('intr_control_noisa.cc')
     Return()
 
 # Only build the protocol buffer instructions tracer if we have protobuf support
@@ -97,7 +94,6 @@ SimObject('CheckerCPU.py')
 SimObject('BaseCPU.py')
 SimObject('CPUTracers.py')
 SimObject('FuncUnit.py')
-SimObject('IntrControl.py')
 SimObject('TimingExpr.py')
 
 Source('activity.cc')
@@ -105,7 +101,6 @@ Source('base.cc')
 Source('exetrace.cc')
 Source('func_unit.cc')
 Source('inteltrace.cc')
-Source('intr_control.cc')
 Source('nativetrace.cc')
 Source('profile.cc')
 Source('reg_class.cc')