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inorder/dtb: make sure DTB translate correct address

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The DTB expects the correct PC in the ThreadContext
but how if the memory accesses are speculative? Shouldn't
we send along the requestor's PC to the translate functions?
This commit is contained in:
Korey Sewell
2011-06-19 21:43:41 -04:00
parent 716e447da8
commit 5ef0b7a9db
2 changed files with 10 additions and 3 deletions
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2
src/arch/alpha/tlb.cc
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@@ -457,7 +457,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
}
if (PcPAL(tc->pcState().pc())) {
if (PcPAL(req->getPC())) {
mode = (req->getFlags() & Request::ALTMODE) ?
(mode_type)ALT_MODE_AM(
tc->readMiscRegNoEffect(IPR_ALT_MODE))

11
src/cpu/inorder/resources/cache_unit.cc
View File

@@ -426,9 +426,16 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
ThreadID tid = inst->readTid();
setupMemRequest(inst, cache_req, acc_size, flags);
//@todo: HACK: the DTB expects the correct PC in the ThreadContext
// but how if the memory accesses are speculative? Shouldn't
// we send along the requestor's PC to the translate functions?
ThreadContext *tc = cpu->thread[tid]->getTC();
PCState old_pc = tc->pcState();
tc->pcState() = inst->pcState();
inst->fault =
_tlb->translateAtomic(cache_req->memReq,
cpu->thread[tid]->getTC(), tlb_mode);
_tlb->translateAtomic(cache_req->memReq, tc, tlb_mode);
tc->pcState() = old_pc;
if (inst->fault != NoFault) {
DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating "