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arch-riscv: Check FPU status for c.flwsp c.fldsp c.fswsp c.fsdsp

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The change adds the missing FPU checking for these instructions.

Change-Id: I7f2ef89786af0d528f2029f1097cfeac6c7d65f2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71198
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Roger Chang
2023-06-02 17:00:59 +08:00
parent 917ced812c
commit 5e5e81d1c5
1 changed files with 20 additions and 0 deletions
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20
src/arch/riscv/isa/decoder.isa
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@@ -307,6 +307,11 @@ decode QUADRANT default Unknown::unknown() {
CIMM1 << 5 |
CIMM5<2:0> << 6;
}}, {{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
Fc1_bits = Mem;
}}, {{
EA = rvZext(sp + offset);
@@ -330,6 +335,11 @@ decode QUADRANT default Unknown::unknown() {
CIMM1 << 5 |
CIMM5<1:0> << 6;
}}, {{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
freg_t fd;
fd = freg(f32(Mem_uw));
Fd_bits = fd.v;
@@ -387,6 +397,11 @@ decode QUADRANT default Unknown::unknown() {
offset = CIMM6<5:3> << 3 |
CIMM6<2:0> << 6;
}}, {{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
Mem_ud = Fc2_bits;
}}, {{
EA = rvZext(sp + offset);
@@ -404,6 +419,11 @@ decode QUADRANT default Unknown::unknown() {
offset = CIMM6<5:2> << 2 |
CIMM6<1:0> << 6;
}}, {{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
Mem_uw = unboxF32(boxF32(Fs2_bits));
}}, {{
EA = (uint32_t)(sp_uw + offset);