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arch-riscv: Fix GDB connection failed after #1099 (#1152)

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GDB connection failed after the PR[1] changed the index of CSR_FCSR to
MISCREG_FCSR itself. It cause the out of bound error.

[1]: https://github.com/gem5/gem5/pull/1099

gem5 issue: https://github.com/gem5/gem5/issues/1151
Change-Id: I402febe5a3a9addf3d4821ad716ade14e227d5d7
This commit is contained in:
Yu-Cheng Chang
2024-05-22 00:58:15 +08:00
committed by GitHub
parent 0824d7f2cd
commit 5e20438c1c
1 changed files with 4 additions and 4 deletions
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8
src/arch/riscv/remote_gdb.cc
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@@ -253,7 +253,7 @@ RemoteGDB::Riscv32GdbRegCache::getRegs(ThreadContext *context)
CSRData.at(CSR_FFLAGS).physIndex) & RVxCSRMasks.at(CSR_FFLAGS);
r.frm = context->readMiscRegNoEffect(
CSRData.at(CSR_FRM).physIndex) & RVxCSRMasks.at(CSR_FRM);
r.fcsr = context->readMiscRegNoEffect(
r.fcsr = context->readMiscReg(
CSRData.at(CSR_FCSR).physIndex) & RVxCSRMasks.at(CSR_FCSR);
// CSR registers
@@ -363,7 +363,7 @@ RemoteGDB::Riscv32GdbRegCache::setRegs(ThreadContext *context) const
setRegNoEffectWithMask(context, RV32, pms, CSR_FFLAGS, r.fflags);
setRegNoEffectWithMask(context, RV32, pms, CSR_FRM, r.frm);
setRegNoEffectWithMask(context, RV32, pms, CSR_FCSR, r.fcsr);
setRegWithMask(context, RV32, pms, CSR_FCSR, r.fcsr);
// TODO: implement CSR counter registers for mcycle(h), minstret(h)
@@ -450,7 +450,7 @@ RemoteGDB::Riscv64GdbRegCache::getRegs(ThreadContext *context)
CSRData.at(CSR_FFLAGS).physIndex) & RVxCSRMasks.at(CSR_FFLAGS);
r.frm = context->readMiscRegNoEffect(
CSRData.at(CSR_FRM).physIndex) & RVxCSRMasks.at(CSR_FRM);
r.fcsr = context->readMiscRegNoEffect(
r.fcsr = context->readMiscReg(
CSRData.at(CSR_FCSR).physIndex) & RVxCSRMasks.at(CSR_FCSR);
// CSR registers
@@ -554,7 +554,7 @@ RemoteGDB::Riscv64GdbRegCache::setRegs(ThreadContext *context) const
setRegNoEffectWithMask(context, RV64, pms, CSR_FFLAGS, r.fflags);
setRegNoEffectWithMask(context, RV64, pms, CSR_FRM, r.frm);
setRegNoEffectWithMask(context, RV64, pms, CSR_FCSR, r.fcsr);
setRegWithMask(context, RV64, pms, CSR_FCSR, r.fcsr);
// TODO: implement CSR counter registers for mcycle, minstret