arch-riscv: enable rudimentary fs simulation

These changes enable a simple binary to be simulated in full system mode.
Additionally, a new fault was implemented.
It is executed once the CPU is initialized.
This fault clears all interrupts and sets the pc to a reset vector.

Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88
Reviewed-on: https://gem5-review.googlesource.com/9061
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

src/arch/riscv/SConscript

@@ -57,10 +57,13 @@ if env['TARGET_ISA'] == 'riscv':
     Source('stacktrace.cc')
     Source('tlb.cc')
     Source('system.cc')
+    Source('utility.cc')
 
     Source('linux/process.cc')
     Source('linux/linux.cc')
 
+    Source('bare_metal/system.cc')
+
     SimObject('RiscvInterrupts.py')
     SimObject('RiscvISA.py')
     SimObject('RiscvTLB.py')