arch-gcn3: Fix s_getpc operand information
s_getpc was currently reporting only a single operand, and was only considering the SSRC operand. However, this instruction' source is implicitly the PC. Because its destination register was never tracked for dependence checking purposes, dependence violations are possible. Change-Id: Ia80b8b3e24d5885f646a9ee41212a2cb35b9ffe6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29954 Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
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committed by
Anthony Gutierrez
parent
a0cfd8da6b
commit
5dc5d23b79
@@ -5846,9 +5846,7 @@ namespace Gcn3ISA
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getOperandSize(int opIdx) override
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{
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switch (opIdx) {
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case 0: //ssrc
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return 8;
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case 1: //sdst
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case 0: //sdst
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return 8;
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default:
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fatal("op idx %i out of bounds\n", opIdx);
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@@ -5860,9 +5858,7 @@ namespace Gcn3ISA
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isSrcOperand(int opIdx) override
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{
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switch (opIdx) {
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case 0: //ssrc
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return true;
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case 1: //sdst
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case 0: //sdst
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return false;
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default:
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fatal("op idx %i out of bounds\n", opIdx);
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@@ -5874,9 +5870,7 @@ namespace Gcn3ISA
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isDstOperand(int opIdx) override
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{
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switch (opIdx) {
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case 0: //ssrc
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return false;
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case 1: //sdst
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case 0: //sdst
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return true;
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default:
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fatal("op idx %i out of bounds\n", opIdx);
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@@ -326,7 +326,12 @@ namespace Gcn3ISA
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switch (opIdx) {
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case 0:
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return isScalarReg(instData.SSRC0);
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if (instData.OP == 0x1C) {
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// Special case for s_getpc, which has no source reg.
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// Instead, it implicitly reads the PC.
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return isScalarReg(instData.SDST);
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}
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return isScalarReg(instData.SSRC0);
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case 1:
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return isScalarReg(instData.SDST);
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default:
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@@ -353,6 +358,12 @@ namespace Gcn3ISA
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switch (opIdx) {
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case 0:
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if (instData.OP == 0x1C) {
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// Special case for s_getpc, which has no source reg.
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// Instead, it implicitly reads the PC.
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return opSelectorToRegIdx(instData.SDST,
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gpuDynInst->wavefront()->reservedScalarRegs);
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}
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return opSelectorToRegIdx(instData.SSRC0,
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gpuDynInst->wavefront()->reservedScalarRegs);
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case 1:
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