misc: Updates for gcc7.2 for x86
GCC 7.2 is much stricter than previous GCC versions. The following changes are needed: * There is now a warning if there is an implicit fallthrough between two case statments. C++17 adds the [[fallthrough]]; declaration. However, to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH. M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and if that doesn't exist, it defaults to nothing (no older compilers generate warnings). * The above resulted in a couple of bugs that were found. This is noted in the review request on gerrit. * throw() for dynamic exception specification is deprecated * There were a couple of new uninitialized variable warnings * Can no longer perform bitwise operations on a bool. * Must now include <functional> for std::function * Compiler bug for void* lambda. Changed to auto as work around. See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878 Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5802 Reviewed-by: Gabe Black <gabeblack@google.com>
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@@ -385,7 +385,7 @@ GenericTimer::setMiscReg(int reg, unsigned cpu, MiscReg val)
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case MISCREG_CNTPS_CVAL_EL1:
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case MISCREG_CNTPS_TVAL_EL1:
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case MISCREG_CNTPS_CTL_EL1:
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/* FALLTHROUGH */
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M5_FALLTHROUGH;
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// PL2 phys. timer, non-secure
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case MISCREG_CNTHCTL:
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@@ -466,7 +466,7 @@ GenericTimer::readMiscReg(int reg, unsigned cpu)
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case MISCREG_CNTPS_CVAL_EL1:
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case MISCREG_CNTPS_TVAL_EL1:
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case MISCREG_CNTPS_CTL_EL1:
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/* FALLTHROUGH */
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M5_FALLTHROUGH;
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// PL2 phys. timer, non-secure
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case MISCREG_CNTHCTL:
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@@ -2290,14 +2290,13 @@ IGbE::rxStateMachine()
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int descLeft = rxDescCache.descLeft();
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DPRINTF(EthernetSM, "RXS: descLeft: %d rdmts: %d rdlen: %d\n",
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descLeft, regs.rctl.rdmts(), regs.rdlen());
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switch (regs.rctl.rdmts()) {
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case 2: if (descLeft > .125 * regs.rdlen()) break;
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case 1: if (descLeft > .250 * regs.rdlen()) break;
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case 0: if (descLeft > .500 * regs.rdlen()) break;
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// rdmts 2->1/8, 1->1/4, 0->1/2
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int ratio = (1ULL << (regs.rctl.rdmts() + 1));
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if (descLeft * ratio <= regs.rdlen()) {
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DPRINTF(Ethernet, "RXS: Interrupting (RXDMT) "
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"because of descriptors left\n");
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postInterrupt(IT_RXDMT);
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break;
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}
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if (rxFifo.empty())
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@@ -249,7 +249,7 @@ CopyEngine::CopyEngineChannel::channelRead(Packet *pkt, Addr daddr, int size)
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break;
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case CHAN_STATUS:
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assert(size == sizeof(uint64_t));
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pkt->set<uint64_t>(cr.status() | ~busy);
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pkt->set<uint64_t>(cr.status() | (busy ? 0 : 1));
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break;
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case CHAN_CHAINADDR:
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assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
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@@ -705,6 +705,7 @@ IdeDisk::startCommand()
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// Supported DMA commands
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case WDCC_WRITEDMA:
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dmaRead = true; // a write to the disk is a DMA read from memory
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M5_FALLTHROUGH;
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case WDCC_READDMA:
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if (!(cmdReg.drive & DRIVE_LBA_BIT))
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panic("Attempt to perform CHS access, only supports LBA\n");
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@@ -455,10 +455,12 @@ X86ISA::I8042::write(PacketPtr pkt)
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case WriteOutputPort:
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warn("i8042 \"Write output port\" command not implemented.\n");
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lastCommand = WriteOutputPort;
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break;
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case WriteKeyboardOutputBuff:
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warn("i8042 \"Write keyboard output buffer\" "
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"command not implemented.\n");
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lastCommand = WriteKeyboardOutputBuff;
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break;
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case WriteMouseOutputBuff:
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DPRINTF(I8042, "Got command to write to mouse output buffer.\n");
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lastCommand = WriteMouseOutputBuff;
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