mem-ruby: replace desks, add desc where required
Events in *.sm are required to have "desc" defined. JIRA: https://gem5.atlassian.net/browse/GEM5-999 Change-Id: I95f59c422bdd264a9e1077b75bf7a0e9f39685aa Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46119 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Hoa Nguyen
@@ -114,7 +114,7 @@ machine(MachineType:Directory, "Directory protocol")
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DMA_WRITE_PARTIAL, desc="DMA Write partial line";
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DMA_ACK, desc="DMA Ack";
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Data, desc="Data to directory";
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All_Acks, desk="All pending acks, unblocks, etc have been received";
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All_Acks, desc="All pending acks, unblocks, etc have been received";
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}
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// TYPES
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@@ -206,7 +206,7 @@ machine(MachineType:Cache, "Cache coherency protocol") :
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state_declaration(State, default="Cache_State_null") {
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// Stable states
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I, AccessPermission:Invalid, desk="Invalid / not present locally or upstream";
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I, AccessPermission:Invalid, desc="Invalid / not present locally or upstream";
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// States when block is present in local cache only
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SC, AccessPermission:Read_Only, desc="Shared Clean";
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@@ -216,21 +216,21 @@ machine(MachineType:Cache, "Cache coherency protocol") :
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UD_T, AccessPermission:Read_Write, desc="UD with use timeout";
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// Invalid in local cache but present in upstream caches
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RU, AccessPermission:Invalid, desk="Upstream requester has line in UD/UC";
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RSC, AccessPermission:Invalid, desk="Upstream requester has line in SC";
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RSD, AccessPermission:Invalid, desk="Upstream requester has line in SD and maybe SC";
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RUSC, AccessPermission:Invalid, desk="RSC + this node stills has exclusive access";
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RUSD, AccessPermission:Invalid, desk="RSD + this node stills has exclusive access";
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RU, AccessPermission:Invalid, desc="Upstream requester has line in UD/UC";
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RSC, AccessPermission:Invalid, desc="Upstream requester has line in SC";
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RSD, AccessPermission:Invalid, desc="Upstream requester has line in SD and maybe SC";
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RUSC, AccessPermission:Invalid, desc="RSC + this node stills has exclusive access";
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RUSD, AccessPermission:Invalid, desc="RSD + this node stills has exclusive access";
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// Both in local and upstream caches. In some cases local maybe stale
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SC_RSC, AccessPermission:Read_Only, desk="SC + RSC";
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SD_RSC, AccessPermission:Read_Only, desk="SD + RSC";
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SD_RSD, AccessPermission:Read_Only, desk="SD + RSD";
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UC_RSC, AccessPermission:Read_Write, desk="UC + RSC";
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UC_RU, AccessPermission:Invalid, desk="UC + RU";
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UD_RU, AccessPermission:Invalid, desk="UD + RU";
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UD_RSD, AccessPermission:Read_Write, desk="UD + RSD";
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UD_RSC, AccessPermission:Read_Write, desk="UD + RSC";
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SC_RSC, AccessPermission:Read_Only, desc="SC + RSC";
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SD_RSC, AccessPermission:Read_Only, desc="SD + RSC";
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SD_RSD, AccessPermission:Read_Only, desc="SD + RSD";
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UC_RSC, AccessPermission:Read_Write, desc="UC + RSC";
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UC_RU, AccessPermission:Invalid, desc="UC + RU";
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UD_RU, AccessPermission:Invalid, desc="UD + RU";
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UD_RSD, AccessPermission:Read_Write, desc="UD + RSD";
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UD_RSC, AccessPermission:Read_Write, desc="UD + RSC";
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// Generic transient state
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// There is only a transient "BUSY" state. The actions taken at this state
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@@ -261,90 +261,90 @@ machine(MachineType:Cache, "Cache coherency protocol") :
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// Events triggered by sequencer requests or snoops in the rdy queue
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// See CHIRequestType in CHi-msg.sm for descriptions
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Load;
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Store;
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Prefetch;
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ReadShared;
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ReadNotSharedDirty;
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ReadUnique;
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ReadUnique_PoC;
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ReadOnce;
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CleanUnique;
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Evict;
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WriteBackFull;
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WriteEvictFull;
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WriteCleanFull;
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WriteUnique;
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WriteUniquePtl_PoC;
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WriteUniqueFull_PoC;
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WriteUniqueFull_PoC_Alloc;
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SnpCleanInvalid;
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SnpShared;
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SnpSharedFwd;
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SnpNotSharedDirtyFwd;
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SnpUnique;
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SnpUniqueFwd;
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SnpOnce;
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SnpOnceFwd;
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SnpStalled; // A snoop stall triggered from the inport
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Load, desc="";
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Store, desc="";
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Prefetch, desc="";
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ReadShared, desc="";
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ReadNotSharedDirty, desc="";
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ReadUnique, desc="";
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ReadUnique_PoC, desc="";
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ReadOnce, desc="";
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CleanUnique, desc="";
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Evict, desc="";
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WriteBackFull, desc="";
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WriteEvictFull, desc="";
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WriteCleanFull, desc="";
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WriteUnique, desc="";
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WriteUniquePtl_PoC, desc="";
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WriteUniqueFull_PoC, desc="";
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WriteUniqueFull_PoC_Alloc, desc="";
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SnpCleanInvalid, desc="";
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SnpShared, desc="";
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SnpSharedFwd, desc="";
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SnpNotSharedDirtyFwd, desc="";
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SnpUnique, desc="";
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SnpUniqueFwd, desc="";
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SnpOnce, desc="";
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SnpOnceFwd, desc="";
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SnpStalled, desc=""; // A snoop stall triggered from the inport
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// Events triggered by incoming response messages
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// See CHIResponseType in CHi-msg.sm for descriptions
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CompAck;
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Comp_I;
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Comp_UC;
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Comp_SC;
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CompDBIDResp;
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DBIDResp;
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Comp;
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ReadReceipt;
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RespSepData;
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SnpResp_I;
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SnpResp_I_Fwded_UC;
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SnpResp_I_Fwded_UD_PD;
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SnpResp_SC;
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SnpResp_SC_Fwded_SC;
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SnpResp_SC_Fwded_SD_PD;
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SnpResp_UC_Fwded_I;
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SnpResp_UD_Fwded_I;
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SnpResp_SC_Fwded_I;
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SnpResp_SD_Fwded_I;
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RetryAck;
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RetryAck_PoC;
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PCrdGrant;
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PCrdGrant_PoC;
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RetryAck_Hazard;
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RetryAck_PoC_Hazard;
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PCrdGrant_Hazard;
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PCrdGrant_PoC_Hazard;
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CompAck, desc="";
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Comp_I, desc="";
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Comp_UC, desc="";
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Comp_SC, desc="";
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CompDBIDResp, desc="";
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DBIDResp, desc="";
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Comp, desc="";
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ReadReceipt, desc="";
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RespSepData, desc="";
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SnpResp_I, desc="";
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SnpResp_I_Fwded_UC, desc="";
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SnpResp_I_Fwded_UD_PD, desc="";
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SnpResp_SC, desc="";
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SnpResp_SC_Fwded_SC, desc="";
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SnpResp_SC_Fwded_SD_PD, desc="";
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SnpResp_UC_Fwded_I, desc="";
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SnpResp_UD_Fwded_I, desc="";
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SnpResp_SC_Fwded_I, desc="";
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SnpResp_SD_Fwded_I, desc="";
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RetryAck, desc="";
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RetryAck_PoC, desc="";
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PCrdGrant, desc="";
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PCrdGrant_PoC, desc="";
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RetryAck_Hazard, desc="";
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RetryAck_PoC_Hazard, desc="";
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PCrdGrant_Hazard, desc="";
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PCrdGrant_PoC_Hazard, desc="";
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// Events triggered by incoming data response messages
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// See CHIDataType in CHi-msg.sm for descriptions
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CompData_I;
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CompData_UC;
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CompData_SC;
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CompData_UD_PD;
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CompData_SD_PD;
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DataSepResp_UC;
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CBWrData_I;
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CBWrData_UC;
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CBWrData_SC;
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CBWrData_UD_PD;
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CBWrData_SD_PD;
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NCBWrData;
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SnpRespData_I;
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SnpRespData_I_PD;
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SnpRespData_SC;
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SnpRespData_SC_PD;
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SnpRespData_SD;
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SnpRespData_UC;
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SnpRespData_UD;
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SnpRespData_SC_Fwded_SC;
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SnpRespData_SC_Fwded_SD_PD;
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SnpRespData_SC_PD_Fwded_SC;
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SnpRespData_I_Fwded_SD_PD;
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SnpRespData_I_PD_Fwded_SC;
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SnpRespData_I_Fwded_SC;
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CompData_I, desc="";
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CompData_UC, desc="";
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CompData_SC, desc="";
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CompData_UD_PD, desc="";
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CompData_SD_PD, desc="";
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DataSepResp_UC, desc="";
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CBWrData_I, desc="";
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CBWrData_UC, desc="";
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CBWrData_SC, desc="";
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CBWrData_UD_PD, desc="";
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CBWrData_SD_PD, desc="";
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NCBWrData, desc="";
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SnpRespData_I, desc="";
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SnpRespData_I_PD, desc="";
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SnpRespData_SC, desc="";
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SnpRespData_SC_PD, desc="";
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SnpRespData_SD, desc="";
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SnpRespData_UC, desc="";
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SnpRespData_UD, desc="";
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SnpRespData_SC_Fwded_SC, desc="";
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SnpRespData_SC_Fwded_SD_PD, desc="";
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SnpRespData_SC_PD_Fwded_SC, desc="";
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SnpRespData_I_Fwded_SD_PD, desc="";
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SnpRespData_I_PD_Fwded_SC, desc="";
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SnpRespData_I_Fwded_SC, desc="";
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// We use special events for requests that we detect to be stale. This is
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// done for debugging only. We sent a stale response so the requester can
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@@ -352,10 +352,10 @@ machine(MachineType:Cache, "Cache coherency protocol") :
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// A Write or Evict becomes stale when the requester receives a snoop that
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// changes the state of the data while the request was pending.
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// Actual CHI implementations don't have this check.
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Evict_Stale;
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WriteBackFull_Stale;
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WriteEvictFull_Stale;
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WriteCleanFull_Stale;
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Evict_Stale, desc="";
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WriteBackFull_Stale, desc="";
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WriteEvictFull_Stale, desc="";
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WriteCleanFull_Stale, desc="";
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// Cache fill handling
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CheckCacheFill, desc="Check if need to write or update the cache and trigger any necessary allocation and evictions";
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@@ -474,9 +474,9 @@ machine(MachineType:Cache, "Cache coherency protocol") :
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// any queued action and is not expecting responses/data. The transaction
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// is finalized and the next stable state is stored in the cache/directory
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// See the processNextState and makeFinalState functions
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Final;
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Final, desc="";
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null;
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null, desc="";
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}
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////////////////////////////////////////////////////////////////////////////
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@@ -80,7 +80,7 @@ machine(MachineType:Memory, "Memory controller interface") :
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state_declaration(State, desc="Transaction states", default="Memory_State_READY") {
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// We don't know if the line is cached, so the memory copy is maybe stable
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READY, AccessPermission:Backing_Store, desk="Ready to transfer the line";
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READY, AccessPermission:Backing_Store, desc="Ready to transfer the line";
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WAITING_NET_DATA, AccessPermission:Backing_Store_Busy, desc="Waiting data from the network";
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SENDING_NET_DATA, AccessPermission:Backing_Store_Busy, desc="Sending data to the network";
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@@ -97,28 +97,28 @@ machine(MachineType:Memory, "Memory controller interface") :
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enumeration(Event, desc="Memory events") {
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// Checks if a request can allocate a TBE be moved to reqRdy
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CheckAllocTBE;
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CheckAllocTBE_WithCredit;
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CheckAllocTBE, desc="";
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CheckAllocTBE_WithCredit, desc="";
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// Requests
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WriteNoSnpPtl;
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WriteNoSnp;
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ReadNoSnp;
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ReadNoSnpSep;
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WriteNoSnpPtl, desc="";
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WriteNoSnp, desc="";
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ReadNoSnp, desc="";
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ReadNoSnpSep, desc="";
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// Data
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WriteData;
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WriteData, desc="";
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// Memory side
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MemoryData;
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MemoryAck;
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MemoryData, desc="";
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MemoryAck, desc="";
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// Internal event triggers
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Trigger_Send;
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Trigger_SendDone;
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Trigger_ReceiveDone;
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Trigger_SendRetry;
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Trigger_SendPCrdGrant;
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Trigger_Send, desc="";
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Trigger_SendDone, desc="";
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Trigger_ReceiveDone, desc="";
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Trigger_SendRetry, desc="";
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Trigger_SendPCrdGrant, desc="";
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}
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