[mq]: sefssparcregfile.patch

src/arch/sparc/SConscript

@@ -40,6 +40,7 @@ if env['TARGET_ISA'] == 'sparc':
     Source('pagetable.cc')
     Source('remote_gdb.cc')
     Source('tlb.cc')
+    Source('ua2005.cc')
     Source('utility.cc')
 
     SimObject('SparcInterrupts.py')
@@ -53,7 +54,6 @@ if env['TARGET_ISA'] == 'sparc':
         SimObject('SparcSystem.py')
 
         Source('system.cc')
-        Source('ua2005.cc')
         Source('vtophys.cc')
     else:
         Source('process.cc')

src/arch/sparc/isa.cc

@@ -136,12 +136,10 @@ ISA::clear()
     nres_error_head = 0;
     nres_error_tail = 0;
 
-#if FULL_SYSTEM
     // If one of these events is active, it's not obvious to me how to get
     // rid of it cleanly. For now we'll just assert that they're not.
     if (tickCompare != NULL && sTickCompare != NULL && hSTickCompare != NULL)
         panic("Tick comparison event active when clearing the ISA object.\n");
-#endif
 }
 
 MiscReg
@@ -346,20 +344,8 @@ ISA::readMiscReg(int miscReg, ThreadContext * tc)
       case MISCREG_QUEUE_RES_ERROR_TAIL:
       case MISCREG_QUEUE_NRES_ERROR_HEAD:
       case MISCREG_QUEUE_NRES_ERROR_TAIL:
-#if FULL_SYSTEM
       case MISCREG_HPSTATE:
         return readFSReg(miscReg, tc);
-#else
-      case MISCREG_HPSTATE:
-        // HPSTATE is special because because sometimes in privilege
-        // checks for instructions it will read HPSTATE to make sure
-        // the priv. level is ok So, we'll just have to tell it it
-        // isn't, instead of panicing.
-        return 0;
-
-      panic("Accessing Fullsystem register %d in SE mode\n", miscReg);
-#endif
-
     }
     return readMiscRegNoEffect(miscReg);
 }
@@ -569,12 +555,10 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
         return;
       case MISCREG_TL:
         tl = val;
-#if FULL_SYSTEM
         if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
             tc->getCpuPtr()->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
         else
             tc->getCpuPtr()->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
-#endif
         return;
       case MISCREG_CWP:
         new_val = val >= NWindows ? NWindows - 1 : val;
@@ -610,18 +594,9 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
       case MISCREG_QUEUE_RES_ERROR_TAIL:
       case MISCREG_QUEUE_NRES_ERROR_HEAD:
       case MISCREG_QUEUE_NRES_ERROR_TAIL:
-#if FULL_SYSTEM
       case MISCREG_HPSTATE:
         setFSReg(miscReg, val, tc);
         return;
-#else
-      case MISCREG_HPSTATE:
-        // HPSTATE is special because normal trap processing saves HPSTATE when
-        // it goes into a trap, and restores it when it returns.
-        return;
-      panic("Accessing Fullsystem register %d to %#x in SE mode\n",
-              miscReg, val);
-#endif
     }
     setMiscRegNoEffect(miscReg, new_val);
 }
@@ -667,7 +642,6 @@ ISA::serialize(EventManager *em, std::ostream &os)
     SERIALIZE_SCALAR(res_error_tail);
     SERIALIZE_SCALAR(nres_error_head);
     SERIALIZE_SCALAR(nres_error_tail);
-#if FULL_SYSTEM
     Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
     ThreadContext *tc = NULL;
     BaseCPU *cpu = NULL;
@@ -701,7 +675,6 @@ ISA::serialize(EventManager *em, std::ostream &os)
         SERIALIZE_SCALAR(stick_cmp);
         SERIALIZE_SCALAR(hstick_cmp);
     }
-#endif
 }
 
 void
@@ -747,7 +720,6 @@ ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(nres_error_head);
     UNSERIALIZE_SCALAR(nres_error_tail);
 
-#if FULL_SYSTEM
     Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
     ThreadContext *tc = NULL;
     BaseCPU *cpu = NULL;
@@ -778,7 +750,6 @@ ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
         }
     }
 
- #endif
 }
 
 }

src/arch/sparc/isa.hh

@@ -114,7 +114,6 @@ class ISA
 
     // These need to check the int_dis field and if 0 then
     // set appropriate bit in softint and checkinterrutps on the cpu
-#if FULL_SYSTEM
     void  setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
     MiscReg readFSReg(int miscReg, ThreadContext * tc);
 
@@ -138,7 +137,6 @@ class ISA
     typedef CpuEventWrapper<ISA,
             &ISA::processHSTickCompare> HSTickCompareEvent;
     HSTickCompareEvent *hSTickCompare;
-#endif
 
     static const int NumGlobalRegs = 8;
     static const int NumWindowedRegs = 24;
@@ -205,11 +203,9 @@ class ISA
 
     ISA()
     {
-#if FULL_SYSTEM
         tickCompare = NULL;
         sTickCompare = NULL;
         hSTickCompare = NULL;
-#endif
 
         clear();
     }

src/arch/sparc/ua2005.cc

@@ -207,12 +207,10 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
       case MISCREG_HPSTATE:
         // T1000 spec says impl. dependent val must always be 1
         setMiscRegNoEffect(miscReg, val | HPSTATE::id);
-#if FULL_SYSTEM
         if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
             cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
         else
             cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
-#endif
         break;
       case MISCREG_HTSTATE:
         setMiscRegNoEffect(miscReg, val);
@@ -226,8 +224,10 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
             DPRINTF(Quiesce, "Cpu executed quiescing instruction\n");
             // Time to go to sleep
             tc->suspend();
+#if FULL_SYSTEM
             if (tc->getKernelStats())
                 tc->getKernelStats()->quiesce();
+#endif
         }
         break;