tests: Add memory traffic generation tests

These test the gem5 components memory components via a traffic
generator.

Change-Id: Ifba78a6f4a062102da72c88f4df70b2e7fee0888
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49559
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

tests/gem5/configs/components-library/simple_traffic_run.py

@@ -25,10 +25,9 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 """
-This script creates a simple traffic generator.
-
-The simulator starts with a linear traffic generator, and ends with a random
-traffic generator.
+This script creates a simple traffic generator. The simulator starts with a
+linear traffic generator, and ends with a random traffic generator. It is used
+for testing purposes.
 """
 
 import m5
@@ -37,6 +36,8 @@ from m5.objects import Root
 
 import sys
 import os
+import argparse
+import importlib
 
 # This is a lame hack to get the imports working correctly.
 # TODO: This needs fixed.
@@ -52,15 +53,40 @@ sys.path.append(
 
 from components_library.boards.test_board import TestBoard
 from components_library.cachehierarchies.classic.no_cache import NoCache
-from components_library.memory.single_channel import SingleChannelDDR3_1600
+from components_library.memory.single_channel import *
 from components_library.processors.complex_generator import ComplexGenerator
 
+parser = argparse.ArgumentParser(
+    description="A traffic generator that can be used to test a gem5 "
+    "memory component."
+)
+
+parser.add_argument(
+    "module",
+    type=str,
+    help="The python module to import.",
+)
+
+parser.add_argument(
+    "mem_class",
+    type=str,
+    help="The memory class to import and instantiate.",
+)
+
+parser.add_argument(
+    "arguments",
+    nargs="*",
+    help="The arguments needed to instantiate the memory class.",
+)
+
+args = parser.parse_args()
+
 # This setup does not require a cache heirarchy. We therefore use the `NoCache`
 # setup.
 cache_hierarchy = NoCache()
 
-# We test a Single Channel DDR3_1600.
-memory = SingleChannelDDR3_1600(size="512MiB")
+memory_class = getattr(importlib.import_module(args.module), args.mem_class)
+memory = memory_class(*args.arguments)
 
 cmxgen = ComplexGenerator(num_cores=1)
 cmxgen.add_linear(rate="100GB/s")

tests/gem5/traffic_gen/test_memory_traffic_gen.py

@@ -0,0 +1,84 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+This tests the gem5 components library memory components with a simple traffic
+generator.
+
+TODO: At present all the Single Channel memory components are tested. This
+      should be expanded to included DRAMSIM3 memory systems.
+"""
+
+from testlib import *
+
+
+def test_memory(module: str, memory: str, *args) -> None:
+    gem5_verify_config(
+        name="test-memory-" + module + "." + memory,
+        fixtures=(),
+        verifiers=(),
+        config=joinpath(
+            config.base_dir,
+            "tests",
+            "gem5",
+            "configs",
+            "components-library",
+            "simple_traffic_run.py",
+        ),
+        config_args=[
+            module,
+            memory,
+        ]
+        + list(args),
+        valid_isas=(constants.null_tag,),
+        valid_hosts=constants.supported_hosts,
+        length=constants.quick_tag,
+    )
+
+
+test_memory(
+    "components_library.memory.single_channel",
+    "SingleChannelDDR3_1600",
+    "512MiB",
+)
+test_memory(
+    "components_library.memory.single_channel",
+    "SingleChannelDDR3_2133",
+    "512MiB",
+)
+test_memory(
+    "components_library.memory.single_channel",
+    "SingleChannelDDR4_2400",
+    "512MiB",
+)
+test_memory(
+    "components_library.memory.single_channel",
+    "SingleChannelLPDDR3_1600",
+    "512MiB",
+)
+test_memory(
+    "components_library.memory.single_channel", "SingleChannelHBM", "512MiB"
+)