arch,base,mem,sim: Fix style in base/types.hh and remove extra includes.

The base/refcnt.hh header was not used in base/types.hh at all, and
enum/ByteOrder.hh was there just so other files could find it. Instead,
this change moves enum/Byteorder.hh to sim/byteswap.hh where it's fits
with the purpose of the header.

This change also fixes some style problems with the code in
base/types.hh itself.

Change-Id: I471ae5cb2cca9169ba8616fb8411b40108a3ffb2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39855
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/freebsd/freebsd.hh

@@ -34,6 +34,7 @@
 #define __ARCH_ARM_FREEBSD_FREEBSD_HH__
 
 #include "kern/freebsd/freebsd.hh"
+#include "sim/byteswap.hh"
 
 class ArmFreebsd : public FreeBSD
 {

src/arch/arm/isa_traits.hh

@@ -43,6 +43,7 @@
 #define __ARCH_ARM_ISA_TRAITS_HH__
 
 #include "base/types.hh"
+#include "sim/byteswap.hh"
 
 namespace ArmISA
 {

src/arch/mips/isa_traits.hh

@@ -31,6 +31,7 @@
 #define __ARCH_MIPS_ISA_TRAITS_HH__
 
 #include "base/types.hh"
+#include "sim/byteswap.hh"
 
 namespace MipsISA
 {

src/arch/power/isa_traits.hh

@@ -32,6 +32,7 @@
 #define __ARCH_POWER_ISA_TRAITS_HH__
 
 #include "base/types.hh"
+#include "sim/byteswap.hh"
 
 namespace PowerISA
 {

src/arch/riscv/isa_traits.hh

@@ -43,6 +43,7 @@
 #define __ARCH_RISCV_ISA_TRAITS_HH__
 
 #include "base/types.hh"
+#include "sim/byteswap.hh"
 
 namespace RiscvISA
 {

src/arch/sparc/isa_traits.hh

@@ -30,6 +30,7 @@
 #define __ARCH_SPARC_ISA_TRAITS_HH__
 
 #include "base/types.hh"
+#include "sim/byteswap.hh"
 
 namespace SparcISA
 {

src/arch/sparc/solaris/solaris.hh

@@ -30,6 +30,7 @@
 #define __ARCH_SPARC_SOLARIS_SOLARIS_HH__
 
 #include "kern/solaris/solaris.hh"
+#include "sim/byteswap.hh"
 
 class SparcSolaris : public Solaris
 {

src/arch/x86/isa_traits.hh

@@ -39,6 +39,7 @@
 #define __ARCH_X86_ISATRAITS_HH__
 
 #include "base/types.hh"
+#include "sim/byteswap.hh"
 
 namespace X86ISA
 {

src/base/pixel.hh

@@ -47,6 +47,7 @@
 #include "base/cprintf.hh"
 #include "base/str.hh"
 #include "base/types.hh"
+#include "sim/byteswap.hh"
 
 /**
  * Internal gem5 representation of a Pixel.

src/base/types.hh

@@ -42,10 +42,6 @@
 #include <ostream>
 #include <stdexcept>
 
-#include "base/refcnt.hh"
-/* Hide the fact that this enum is generated by Python */
-#include "enums/ByteOrder.hh"
-
 /** uint64_t constant */
 #define ULL(N)          ((uint64_t)N##ULL)
 /** int64_t constant */
@@ -100,35 +96,45 @@ class Cycles
     constexpr operator uint64_t() const { return c; }
 
     /** Prefix increment operator. */
-    Cycles& operator++()
-    { ++c; return *this; }
+    Cycles& operator++() { ++c; return *this; }
 
     /** Prefix decrement operator. Is only temporarily used in the O3 CPU. */
-    Cycles& operator--()
-    { assert(c != 0); --c; return *this; }
+    Cycles& operator--() { assert(c != 0); --c; return *this; }
 
     /** In-place addition of cycles. */
-    Cycles& operator+=(const Cycles& cc)
-    { c += cc.c; return *this; }
+    Cycles& operator+=(const Cycles& cc) { c += cc.c; return *this; }
 
     /** Greater than comparison used for > Cycles(0). */
-    constexpr bool operator>(const Cycles& cc) const
-    { return c > cc.c; }
+    constexpr bool
+    operator>(const Cycles& cc) const
+    {
+        return c > cc.c;
+    }
 
-    constexpr Cycles operator +(const Cycles& b) const
-    { return Cycles(c + b.c); }
+    constexpr Cycles
+    operator+(const Cycles& b) const
+    {
+        return Cycles(c + b.c);
+    }
 
-    constexpr Cycles operator -(const Cycles& b) const
+    constexpr Cycles
+    operator-(const Cycles& b) const
     {
         return c >= b.c ? Cycles(c - b.c) :
             throw std::invalid_argument("RHS cycle value larger than LHS");
     }
 
-    constexpr Cycles operator <<(const int32_t shift) const
-    { return Cycles(c << shift); }
+    constexpr Cycles
+    operator <<(const int32_t shift) const
+    {
+        return Cycles(c << shift);
+    }
 
-    constexpr Cycles operator >>(const int32_t shift) const
-    { return Cycles(c >> shift); }
+    constexpr Cycles
+    operator >>(const int32_t shift) const
+    {
+        return Cycles(c >> shift);
+    }
 
     friend std::ostream& operator<<(std::ostream &out, const Cycles & cycles);
 };

src/mem/packet.hh

@@ -60,6 +60,7 @@
 #include "base/types.hh"
 #include "mem/htm.hh"
 #include "mem/request.hh"
+#include "sim/byteswap.hh"
 #include "sim/core.hh"
 
 class Packet;

src/sim/byteswap.hh

@@ -35,6 +35,7 @@
 
 #include "base/logging.hh"
 #include "base/types.hh"
+#include "enums/ByteOrder.hh"
 
 // This lets us figure out what the byte order of the host system is
 #if defined(__linux__)