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MIPS: Consolidate the two AddressErrorFault variants.

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This commit is contained in:
Gabe Black
2011-09-19 06:17:20 -07:00
parent 717d4ae930
commit 59d7fc6b26
3 changed files with 12 additions and 38 deletions
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21
src/arch/mips/faults.cc
View File

@@ -61,9 +61,6 @@ template <> FaultVals MipsFault<ResetFault>::vals =
template <> FaultVals MipsFault<AddressErrorFault>::vals =
{ "Address Error", 0x0180 };
template <> FaultVals MipsFault<StoreAddressErrorFault>::vals =
{ "Store Address Error", 0x0180 };
template <> FaultVals MipsFault<SystemCallFault>::vals =
{ "Syscall", 0x0180 };
@@ -176,20 +173,6 @@ IntegerOverflowFault::invoke(ThreadContext *tc, StaticInstPtr inst)
setHandlerPC(HandlerBase, tc);
}
void
StoreAddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
DPRINTF(MipsPRA, "%s encountered.\n", name());
setExceptionState(tc, 0x5);
tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
// Set new PC
Addr HandlerBase;
// Offset 0x180 - General Exception Vector
HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
setHandlerPC(HandlerBase, tc);
}
void
TrapFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
@@ -244,8 +227,8 @@ void
AddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
DPRINTF(MipsPRA, "%s encountered.\n", name());
setExceptionState(tc, 0x4);
tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
setExceptionState(tc, store ? 0x5 : 0x4);
tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
// Set new PC
Addr HandlerBase;

16
src/arch/mips/faults.hh
View File

@@ -93,8 +93,12 @@ class NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt>
class AddressErrorFault : public MipsFault<AddressErrorFault>
{
protected:
Addr vaddr;
bool store;
public:
AddressErrorFault(Addr vaddr) { badVAddr = vaddr; }
AddressErrorFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store)
{}
#if FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
@@ -102,16 +106,6 @@ class AddressErrorFault : public MipsFault<AddressErrorFault>
};
class StoreAddressErrorFault : public MipsFault<StoreAddressErrorFault>
{
public:
StoreAddressErrorFault(Addr vaddr) { badVAddr = vaddr; }
#if FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
#endif
};
static inline Fault genMachineCheckFault()
{
return new MachineCheckFault;

13
src/arch/mips/tlb.cc
View File

@@ -313,7 +313,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
req->setPaddr(KSeg02Phys(vaddr));
if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel ||
misaligned) {
return new AddressErrorFault(vaddr);
return new AddressErrorFault(vaddr, false);
}
} else if(IsKSeg1(vaddr)) {
// Address will not be translated through TLB, set response, and go!
@@ -333,7 +333,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
uint8_t Asid = req->getAsid();
if (misaligned) {
// Unaligned address!
return new AddressErrorFault(vaddr);
return new AddressErrorFault(vaddr, false);
}
PTE *pte = lookup(VPN,Asid);
if (pte != NULL) {
@@ -387,10 +387,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
if (req->getVaddr() & (req->getSize() - 1)) {
DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
req->getSize());
if (write)
return new StoreAddressErrorFault(req->getVaddr());
else
return new AddressErrorFault(req->getVaddr());
return new AddressErrorFault(req->getVaddr(), write);
}
@@ -411,7 +408,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
req->setPaddr(KSeg02Phys(vaddr));
if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel ||
misaligned) {
return new StoreAddressErrorFault(vaddr);
return new AddressErrorFault(vaddr, true);
}
} else if(IsKSeg1(vaddr)) {
// Address will not be translated through TLB, set response, and go!
@@ -429,7 +426,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
uint8_t Asid = req->getAsid();
PTE *pte = lookup(VPN, Asid);
if (misaligned) {
return new StoreAddressErrorFault(vaddr);
return new AddressErrorFault(vaddr, true);
}
if (pte != NULL) {
// Ok, found something