X86: Remove a naming conflict between the register index parameters and the "picked" register values.
--HG-- extra : convert_revision : 7b2c1be509478153ebf396841e4cbeccee3e03d1
This commit is contained in:
Gabe Black
@@ -328,24 +328,24 @@ let {{
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checkCCFlagBits = "checkCondition(ccFlagBits)"
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genCCFlagBits = \
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"ccFlagBits = genFlags(ccFlagBits, ext, DestReg, src1, op2);"
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"ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);"
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genCCFlagBitsSub = \
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"ccFlagBits = genFlags(ccFlagBits, ext, DestReg, src1, ~op2, true);"
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"ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);"
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genCCFlagBitsLogic = '''
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//Don't have genFlags handle the OF or CF bits
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uint64_t mask = CFBit | OFBit;
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ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, src1, op2);
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ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2);
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//If a logic microop wants to set these, it wants to set them to 0.
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ccFlagBits &= ~(CFBit & ext);
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ccFlagBits &= ~(OFBit & ext);
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'''
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regPick = '''
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IntReg src1 = pick(SrcReg1, 0, dataSize);
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IntReg src2 = pick(SrcReg2, 1, dataSize);
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IntReg psrc1 = pick(SrcReg1, 0, dataSize);
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IntReg psrc2 = pick(SrcReg2, 1, dataSize);
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'''
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immPick = '''
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IntReg src1 = pick(SrcReg1, 0, dataSize);
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IntReg psrc1 = pick(SrcReg1, 0, dataSize);
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'''
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@@ -360,7 +360,7 @@ let {{
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# of the code, one with an integer operand, and one with an immediate
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# operand.
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matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
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regCode = regPick + matcher.sub("src2", code)
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regCode = regPick + matcher.sub("psrc2", code)
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immCode = immPick + matcher.sub("imm8", code)
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if not cc:
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@@ -369,7 +369,7 @@ let {{
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flagCode = ""
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condCode = checkCCFlagBits
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regFlagCode = matcher.sub("src2", flagCode)
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regFlagCode = matcher.sub("psrc2", flagCode)
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immFlagCode = matcher.sub("imm8", flagCode)
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class RegOpChild(RegOp):
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@@ -411,7 +411,7 @@ let {{
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# of the code, one with an integer operand, and one with an immediate
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# operand.
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matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
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regCode = regPick + matcher.sub("src2", code)
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regCode = regPick + matcher.sub("psrc2", code)
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immCode = immPick + matcher.sub("imm8", code)
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class RegOpChild(RegOp):
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@@ -468,66 +468,76 @@ let {{
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setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code);
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defineMicroRegOp('Add', 'DestReg = merge(DestReg, src1 + op2, dataSize)')
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defineMicroRegOp('Or', '''
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DPRINTF(X86, "src1 = %#x\\n", src1);
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DPRINTF(X86, "op2 = %#x\\n", op2);
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DestReg = merge(DestReg, src1 | op2, dataSize);
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''',
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defineMicroRegOp('Add', 'DestReg = merge(DestReg, psrc1 + op2, dataSize)')
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defineMicroRegOp('Or', 'DestReg = merge(DestReg, psrc1 | op2, dataSize);',
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flagCode = genCCFlagBitsLogic)
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defineMicroRegOp('Adc', '''
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CCFlagBits flags = ccFlagBits;
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DestReg = merge(DestReg, src1 + op2 + flags.CF, dataSize);
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DestReg = merge(DestReg, psrc1 + op2 + flags.CF, dataSize);
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''')
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defineMicroRegOp('Sbb', '''
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CCFlagBits flags = ccFlagBits;
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DestReg = merge(DestReg, src1 - op2 - flags.CF, dataSize);
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DestReg = merge(DestReg, psrc1 - op2 - flags.CF, dataSize);
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''', flagCode = genCCFlagBitsSub)
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defineMicroRegOp('And', \
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'DestReg = merge(DestReg, src1 & op2, dataSize)', \
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'DestReg = merge(DestReg, psrc1 & op2, dataSize)', \
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flagCode = genCCFlagBitsLogic)
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defineMicroRegOp('Sub', \
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'DestReg = merge(DestReg, src1 - op2, dataSize)', \
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'DestReg = merge(DestReg, psrc1 - op2, dataSize)', \
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flagCode = genCCFlagBitsSub)
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defineMicroRegOp('Xor', \
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'DestReg = merge(DestReg, src1 ^ op2, dataSize)', \
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'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)', \
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flagCode = genCCFlagBitsLogic)
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defineMicroRegOp('Mul1s', '''
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int signPos = (dataSize * 8) / 2 - 1;
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IntReg srcVal1 = src1 | (-bits(src1, signPos) << signPos);
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IntReg srcVal2 = op2 | (-bits(src1, signPos) << signPos);
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IntReg srcVal1 = psrc1 | (-bits(psrc1, signPos) << signPos);
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IntReg srcVal2 = op2 | (-bits(psrc1, signPos) << signPos);
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DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize)
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''')
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defineMicroRegOp('Mul1u', '''
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int halfSize = (dataSize * 8) / 2;
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IntReg srcVal1 = src1 & mask(halfSize);
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IntReg srcVal1 = psrc1 & mask(halfSize);
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IntReg srcVal2 = op2 & mask(halfSize);
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DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize)
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''')
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defineMicroRegOp('Mulel', \
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'DestReg = merge(DestReg, src1 * op2, dataSize)')
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'DestReg = merge(DestReg, psrc1 * op2, dataSize)')
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defineMicroRegOp('Muleh', '''
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int halfSize = (dataSize * 8) / 2;
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uint64_t src1_h = src1 >> halfSize;
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uint64_t src1_l = src1 & mask(halfSize);
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uint64_t src2_h = op2 >> halfSize;
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uint64_t src2_l = op2 & mask(halfSize);
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uint64_t psrc1_h = psrc1 >> halfSize;
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uint64_t psrc1_l = psrc1 & mask(halfSize);
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uint64_t psrc2_h = op2 >> halfSize;
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uint64_t psrc2_l = op2 & mask(halfSize);
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uint64_t result =
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((src1_l * src2_h) >> halfSize) +
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((src1_h * src2_l) >> halfSize) +
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src1_h * src2_h;
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((psrc1_l * psrc2_h) >> halfSize) +
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((psrc1_h * psrc2_l) >> halfSize) +
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psrc1_h * psrc2_h;
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DestReg = merge(DestReg, result, dataSize);
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''')
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defineMicroRegOp('Div1', '''
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int halfSize = (dataSize * 8) / 2;
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IntReg quotient = (psrc1 / op2) & mask(halfSize);
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IntReg remainder = (psrc1 % op2) & mask(halfSize);
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IntReg result = quotient | (remainder << halfSize);
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DestReg = merge(DestReg, result, dataSize);
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''')
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defineMicroRegOp('Divq', '''
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DestReg = merge(DestReg, psrc1 / op2, dataSize);
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''')
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defineMicroRegOp('Divr', '''
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DestReg = merge(DestReg, psrc1 % op2, dataSize);
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''')
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#
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# HACK HACK HACK HACK - Put src1 in here but make it inert to shut up gcc.
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# HACK HACK HACK HACK - Put psrc1 in here but make it inert to shut up gcc.
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#
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defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, src1 * 0 + op2, dataSize)',
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defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, psrc1 * 0 + op2, dataSize)',
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elseCode='DestReg=DestReg;', cc=True)
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# Shift instructions
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defineMicroRegOp('Sll', '''
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uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
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DestReg = merge(DestReg, src1 << shiftAmt, dataSize);
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DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
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''')
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defineMicroRegOp('Srl', '''
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uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
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@@ -535,7 +545,7 @@ let {{
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// is not defined in the C/C++ standard, we have to mask them out
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// to be sure they're zero.
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uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
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DestReg = merge(DestReg, (src1 >> shiftAmt) & logicalMask, dataSize);
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DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
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''')
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defineMicroRegOp('Sra', '''
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uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
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@@ -544,15 +554,15 @@ let {{
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// them manually to be sure.
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uint64_t arithMask =
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-bits(op2, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
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DestReg = merge(DestReg, (src1 >> shiftAmt) | arithMask, dataSize);
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DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
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''')
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defineMicroRegOp('Ror', '''
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uint8_t shiftAmt =
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(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
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if(shiftAmt)
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{
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uint64_t top = src1 << (dataSize * 8 - shiftAmt);
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uint64_t bottom = bits(src1, dataSize * 8, shiftAmt);
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uint64_t top = psrc1 << (dataSize * 8 - shiftAmt);
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uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
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DestReg = merge(DestReg, top | bottom, dataSize);
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}
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else
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@@ -566,8 +576,8 @@ let {{
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CCFlagBits flags = ccFlagBits;
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uint64_t top = flags.CF << (dataSize * 8 - shiftAmt);
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if(shiftAmt > 1)
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top |= src1 << (dataSize * 8 - shiftAmt - 1);
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uint64_t bottom = bits(src1, dataSize * 8, shiftAmt);
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top |= psrc1 << (dataSize * 8 - shiftAmt - 1);
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uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
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DestReg = merge(DestReg, top | bottom, dataSize);
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}
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else
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@@ -578,9 +588,9 @@ let {{
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(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
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if(shiftAmt)
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{
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uint64_t top = src1 << shiftAmt;
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uint64_t top = psrc1 << shiftAmt;
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uint64_t bottom =
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bits(src1, dataSize * 8 - 1, dataSize * 8 - shiftAmt);
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bits(psrc1, dataSize * 8 - 1, dataSize * 8 - shiftAmt);
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DestReg = merge(DestReg, top | bottom, dataSize);
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}
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else
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@@ -592,11 +602,11 @@ let {{
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if(shiftAmt)
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{
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CCFlagBits flags = ccFlagBits;
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uint64_t top = src1 << shiftAmt;
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uint64_t top = psrc1 << shiftAmt;
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uint64_t bottom = flags.CF << (shiftAmt - 1);
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if(shiftAmt > 1)
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bottom |=
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bits(src1, dataSize * 8 - 1,
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bits(psrc1, dataSize * 8 - 1,
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dataSize * 8 - shiftAmt + 1);
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DestReg = merge(DestReg, top | bottom, dataSize);
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}
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@@ -604,15 +614,15 @@ let {{
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DestReg = DestReg;
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''')
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defineMicroRegOpWr('Wrip', 'RIP = src1 + op2', elseCode="RIP = RIP;")
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defineMicroRegOpWr('Wrip', 'RIP = psrc1 + op2', elseCode="RIP = RIP;")
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defineMicroRegOpRd('Rdip', 'DestReg = RIP')
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defineMicroRegOpImm('Sext', '''
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IntReg val = src1;
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IntReg val = psrc1;
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int sign_bit = bits(val, imm8-1, imm8-1);
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val = sign_bit ? (val | ~mask(imm8)) : val;
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DestReg = merge(DestReg, val, dataSize);''')
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defineMicroRegOpImm('Zext', 'DestReg = bits(src1, imm8-1, 0);')
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defineMicroRegOpImm('Zext', 'DestReg = bits(psrc1, imm8-1, 0);')
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}};
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